LC89210 Sanyo Semiconductor Corporation, LC89210 Datasheet
LC89210
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LC89210 Summary of contents
Page 1
... ITU-T V.23, V.21, and Bell 103 • V.17, V.29 (T104), and V.27ter short training • V.33 half duplex • 1800-Hz or 1700-Hz carrier • The LC89210 is a complete data pump on a single chip. • single-voltage power supply — Operating power dissipation: 375 mW (typical) — Low power mode (typical) • ...
Page 2
... TXA1 – TXA2 DIFout Differential output DC offset V (TXA1 – TXA2) OFFout Input resistance Rin RXA Output resistance Rout TXA Load resistance R TXA L Load capacitance C TXA L LC89210 = 5 V (unless otherwise specified) DD Symbol Conditions OUT Pd max Topr Tstg = 5.0 V ± ...
Page 3
... Pin Assignment Host Interface The LC89210 is interfaced to the control processor through a 64-byte dual-port RAM that is shared by the LC89210 and the host. Pin Type SD0 to SD7 I/O System data bus SA0 to SA6 I System address bus SDS (SDR) I System data strobe SR/W (SWR) I System read/write ...
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... This pin must be left open TEST2 This pin must be left open Note: The LC89210 nominal external clock frequency is 29.4912 MHz. This value has a precision of ±5.10 Boundary Scan Interface The LC89210 provides 13 signals for testing. These signals can be used along with the SGS-Thomson ST18932 boundary scan development tools in the product development process to debug application hardware and software ...
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... Symbol V Digital +5 V (pins 9, 25, and 41) DD GND Digital ground (pins 8, 24, and 40) AV Analog +5 V (pin 62) DD AGNDT Analog transmission system ground (pin 64) AGNDR Analog reception system ground (pin 59) Block Diagrams LC89210 Parameter Function Block Diagram Hardware Block Diagram No. 5382-5/10 ...
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... Access inhibition high state 8 Read enable low state 9 Read data access 10 SINTR clear delay 11 Data valid to tristate 12 Note: * The minimum delay the time from the rising edge of NWRITE to the next falling edge on either NREAD or NWRITE. LC89210 Conditions min 70* 45 ...
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... Serial V.24 Interface Timing Parameter Number TXD to CLK setup time 1 TXD to CLK hold time 2 RXD valid to CLK delay time 3 RXD valid to CLK hold time 4 LC89210 Conditions min typ max Unit ns ns 100 ns ns No. 5382-7/10 ...
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... Electrical Circuit Diagrams Oscillator We recommend the use of the following circuit if an overtone crystal oscillator is used in series resonance mode. LC89210 No. 5382-8/10 ...
Page 9
... While the two most important factors influencing the performance of this fax modem are the performance of the LC89210 itself and the appropriateness of the design of the printed circuit board not the purpose of this section to describe all aspects of modem printed circuit board design. Rather, this section presents the following few recommendations ...
Page 10
... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. LC89210 No. 5382-10/10 ...