AD1854 Analog Devices, AD1854 Datasheet
AD1854
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AD1854 Summary of contents
Page 1
... The AD1854 has a very simple but very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers and sample rate converters. ...
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... With A-Weighted Filter (AD1854KRS) Dynamic Range ( kHz, –60 dB Input) No Filter (AD1854JRS) No Filter (AD1854KRS) With A-Weighted Filter (AD1854JRS) With A-Weighted Filter (AD1854KRS) Total Harmonic Distortion + Noise (AD1854JRS) V Total Harmonic Distortion + Noise (AD1854KRS) V Total Harmonic Distortion + Noise (AD1854JRS and AD1854KRS – ...
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... DV = 5 Min 0.4 × t DMP 0.4 × t DMP 20 20 140 MCLK Periods Min Typ ± 0.04 47 0.448 0.552 106/F 0 –3– AD1854 Max Unit 190 Max Unit °C °C 70 °C +125 Max Unit ns ...
Page 4
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1854 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor- mal operation. Power-Down/Reset. The AD1854 is placed in a low power consumption mode when this pin is held LO. The AD1854 is reset on the rising edge of this signal. The serial control port registers are reset to the default values. Connect HI for normal operation. ...
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... LSB is right-justified to an L/RCLK transi- tion. L/RCLK is HI for the left channel, and LO for the right channel. Data is valid on the rising edge of BCLK. Packed mode can be used when the AD1854 is programmed in right- justified mode. Packed mode is shown is Figure 4. Table II. Frequency Mode Settings ...
Page 7
... For those users who do not use the serial control port still possible to mute the AD1854 output by using the MUTE (Pin 23) signal. Note that the serial control port timing is asynchronous to the serial data port timing. Changes made to the attenuator level will be updated on the next edge of the L/RCLK after the CLATCH write pulse as shown in Figure 8 ...
Page 8
... TIME – ns Figure 7. SPI Port Burst Mode Output Drive, Buffering and Loading The AD1854 analog output stage is able to drive a 1 kΩ (in series with 2 nF) load. Power-Down Reset The AD1854 offers two methods for power-down and reset. When the PD/RST input (Pin 24) is asserted LO, the AD1854 is reset ...
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... PD/RST REV. A minimum setup time is t time is t DDH and the minimum bit The power-down/reset timing is shown in Figure 11. The mini- mum reset LO pulse width is t and the DLS accomplish a successful AD1854 reset operation. . The serial data DLH t DBP MSB-1 t DDS MSB t ...
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... NOTE DGND = AGND ZR MCLK/SR SELECT MCLK 44 11.2896 48 12.2880 96 12.2880 AD1854 STEREO DAC DVDD AVDD C3 C2 100nF 100nF OUTPUT BUFFERS AND LP FILTERS R16 DVDD AVDD 2.15k 1.96k 96/48 OUTL– C14 1nF, NP0 384/256 C13 X2MCLK 1nF, NP0 R17 1.96k ...
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... TYPICAL PERFORMANCE Figures 13 through 20 illustrate the typical analog performance of the AD1854 as measured by an Audio Precision System Two. Signal-to-Noise and THD+N performance are shown under a range of conditions. Figure 14 shows the power supply rejection –60 –65 –70 –75 –80 –85 –90 –95 – ...
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... AD1854 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 100 FREQUENCY – kHz Figure 19. Digital Filter Response 0.32 (8.20) 0.29 (7.40) 0.079 (2.0) MAX (0.05) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 120 140 160 ...