ADSP-2141LKS-N1 Analog Devices, ADSP-2141LKS-N1 Datasheet

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... INTERRUPT APPLICATION MEMORY CONTROLLER REGISTERS INTERFACE 26-BITS 32-BITS ADDR DATA PF7/INT_H RAM/ROM One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 ADSP-2141L 24) Kernel Program 16 Security Scratchpad RAM 16 16 IDMA INTERFACE 32 32 PCI OR CARDBUS INTERFACE PUBLIC KEY RNG ACCELERATOR BLOCK ...

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... The Kernel Mode Control subsystem is responsible for enforcing the security perimeter around the cryptographic functions of the ADSP-2141L. The device may operate in either user mode (kernel space is not accessible) or kernel mode (kernel space is accessible given time. When in kernel mode, the kernel RAM and certain protected crypto registers and functions (kernel space) are accessible only to the CGX library firmware ...

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... A full 40 MHz/33 MHz PCI bus interface has been added to the core DSP functions. The 32-bit PCI interface supports both bus master and target modes. The ADSP-2141L is capable of using DMA to directly access data on other PCI entities and pass that data through its encryption/hash engines. ...

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... This section provides an architecture-level description of the unique function blocks within the ADSP-2141L. Memory Map The ADSP-2141L memory map is very similar to that of the ADSP-2183 DSP, except that it includes significantly more off- chip memory addressing, and has additional crypto registers which are accessible to the user. ...

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... Manage the reset function to ensure that sensitive variables in DSP registers are erased. Most of the kernel mode control functions are implemented in the hardware of the ADSP-2141L and are not directly visible to nonkernel applications (user mode). Any attempt by a user mode application program running on the DSP to access a kernel space addresses (PRAM 0x2001 – ...

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... It is designated the DKEK in the CGX API. One of the laser-programmed configuration bits specifies whether red (plaintext) keys are allowed to be loaded into the ADSP- 2141L from a host. If the AllowRedKeyLoad laser bit is not set, keys may only be loaded in their black form. This is useful in systems where export restrictions limit the key length that may be used or where the external storage environment is untrusted ...

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... Multiply Vector, Add Long Vector, etc., are presented via the CGX interface. PCI/Cardbus Interface The ADSP-2141L appears as a target on the PCI Bus as a single contiguous memory space of 128k bytes. In this memory space, the host can access the following: • The unprotected internal crypto registers of the ADSP-2141L • ...

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... ADSP-2141L Interrupt Controller The DSP core of the ADSP-2141L provides a powerful set of interrupt sources. A total of 14 interrupt sources are available, although two pairs are multiplexed, yielding 12 simultaneous sources. Refer to Table I. The ADSP-2141L enhances the existing interrupt controller within the ADSP-218x DSP Core with some additional func- tions related to the crypto functional blocks and the external host bus interfaces ...

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... PIN FUNCTIONS I/O Descriptions This section describes the physical I/O hardware on the ADSP-2141L Input/ Pin Name Pins Output External Memory Bus Address [25: Data [31:0] 32 I/O Interrupts IRQ2 1 I IRQL0 1 I IRQL1 1 I IRQE 1 I Bus Signals BGH 1 O PMS 1 O DMSL ...

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... ADSP-2141L # of Pin Name Pins Flags PF6:0 7 PF7/INT_H 1 Emulator EE 1 EBR 1 EBG 1 ERESET 1 EMS 1 EINT 1 ECLK 1 ELIN 1 ELOUT 1 Serial EEPROM Interface EE_DI 1 EE_DO 1 EE_CS 1 EE_SK 1 Bus Select BUS_MODE 1 BUS_SEL 1 PCI Bus (Dedicated Pins) PCI_CLK 1 PCI_PAR 1 PCI_IRDY 1 PCI_STOP 1 *When DMS is enabled for generation of CMS, the CMS is activated for DSP access to external memory only, NOT for DMA controller accesses. ...

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... Host Bus modes: IDMA or PCI. IDMA Bus Mode The IDMA bus mode operates the same native ADSP- 218x device, as described in this section. The IDMA port provides an efficient means of communication between a host system and the ADSP-2141L. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead ...

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... PCI_CLK BUS_SEL PCI_PAR PCI_IRDY MMAP VDD OR GND PCI_STOP BMODE EE_DI EEPROM *ADDR0 FROM THE ADSP-2141 EE_DO IS NO CONNECT FOR 32-BIT MEMORY. NC EE_CS ADSP-2141 ADDR1 IS WIRED TO RAM A0. EE_SK –12– A0-A21 BYTE MEMORY (BOOT DATA LOADER) CS ADDR 16-BIT I/O SPACE DATA 2048 LOCATIONS ...

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... BYTE MEMORY (BOOT DATA LOADER) CS ADDR 16-BIT I/O SPACE DATA 2048 LOCATIONS CS PROGRAM ADDR OVERLAY MEMORY DATA 8192 SEGMENTS DATA OVERLAY MEMORY 8192 8K 16 SEGMENTS UP TO 32M 32 *ADDR0 FROM THE ADSP-2141 IS NO CONNECT FOR 32-BIT MEMORY. ADSP-2141 ADDR1 IS WIRED TO RAM A0. ...

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... Bus Modes The ADSP-2141L Host Bus may be configured for one of two personalities: IDMA Mode or PCI Bus Mode. The selection of mode is made with two hardware control inputs BUS_MODE and BUS_SEL at boot time. ...

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... COMMAND SUMMARY Approximately 40 CGX Commands are supported in the API to the ADSP-2141L. General Utilities INIT Initializes Secure Kernel and Allow Reconfiguration of the ADSP-2141L DEFAULT Restores Factory Default Settings RANDOM Generates Random Numbers (between 1K and 64K bytes) GET CHIPINFO Returns ADSP-2141L System Information ...

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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2141L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...

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... Three-statable pins: A0–A25, D0–D31, PMS, DMSL, DMSH, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCKL0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0– IAD15, PF0–PF7. 10 Idle refers to ADSP-2141L state of operation during execution of IDLE Instruction. Deasserted pins are driven to either V 11 Current reflects device operating with no output loads. ...

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... PCI Clock (Guaranteed Over Operating Temperature and Digital Supply Range) The ADSP-2141L is targeted for use in PCI add-on I/O slave card designs. It provides a glueless interface to the PCI bus. All bus drivers are compliant with PCI interface electrical switching and drive capability specifications. The ADSP-2141L does not implement the following signals: LOCK, INTB, INTC, INTD, SBO, SDONE, CLKRUN, AD[64:32], C/BE[7:4], REQ64, ACK64, PAR64 ...

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... Figure 9. Output (Top) and Input Timing Measurement Conditions REV TEST t VAL V (3.3V SIGNALING) STEP OUTPUT CURRENT LEAKAGE CURRENT OFF INPUTS V TEST VALID V TL –19– ADSP-2141L Min Max Unit MAX ...

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... ADSP-2141L Parameter Clock Signals and Reset Timing Requirements: t CLKIN Period CKI t CLKIN Width Low CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT High CKOH Control Signals Timing Requirement: RESET Width Low ...

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... IFS IFH the following cycle. (Refer to the Interrupt Controller Operation section in the Program Control chapter of the ADSP-2100 Family User’s Manual for further informa- tion on interrupt servicing.) 2 Edge-sensitive interrupts require pulsewidths greater than 10 ns ...

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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise, the signal will be recognized 1 on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...

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... If wait-state(s) added, then referenced to last wait-state clock interval DMA wait states DSP CLOCK OUT EXT. ADDR (A25–0) EXT. DMSH EXT. DMSL EXT. WR EXT. DATA (D31–0) Figure 13. External Memory Write: ADSP-2141L DMA Initiated REV. 0 25ns (REF @ 40MHz) t ASW CWR WP t WDE – ...

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... If wait-state(s) added, then referenced to last wait-state clock interval DMA wait states DSP CLOCK OUT EXT. ADDR (A25–0) EXT. DMSH EXT. DMSL EXT. RD EXT. DATA (D31–0) Figure 14. External Memory Read – ADSP-2141L DMA Initiated 25ns (REF @ 40MHz ASR CRD t RDD – ...

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... If wait-state(s) added, then referenced to last wait-state clock interval DSP wait states DSP CLOCK OUT EXT. ADDR (A13–0) PMS, DMSx, BMS, IOMS, CMS EXT. WR EXT. DATA (D23–0) Figure 15. External Memory Write: ADSP-2141L DSP Initiated REV. 0 25ns (REF @ 40MHz) t ASW CWR WP t WDE – ...

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... DSP wait state DSP CLOCK OUT EXT. ADDR (A13–0) PMS, DMSx, BMS, IOMS, CMS EXT. RD EXT. DATA (D23–0) Figure 16. External Memory Read – ADSP-2141L DSP Initiated 25ns (REF @ 40MHz ASR t t CRD RP t RDD –26– ...

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... SCS SCH SCDV SCDD t t SCDE SCDH t TDE t TDV t RDV t TDE t TDV t RDV Figure 17. Serial Ports –27– ADSP-2141L Min Max 0.25t 0.25t + SCK t t SCP SCP Unit ns ns ...

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... ADSP-2141L Parameter IDMA Address Latch (IDMA Mode Multiplex Bus) Timing Requirements: t Duration of Address Latch IALP t MPLX_BUS Address Setup Before Address Latch End IASU t MPLX_BUS Address Hold After Address Latch End IAH t MPLX9 Low Before Start of Address Latch IKA t Start of Write or Read After Address Latch End ...

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... IWR MPLX6 / MPLX_BUS IAD15–0 Figure 19. IDMA Write, Short Write Cycle (IDMA Mode, Multiplex Bus) REV. 0 Min IDSU IDH , t IKSU IKH. t IKW t IKHW t IWP t IDH t IDSU DATA –29– ADSP-2141L Max Unit ...

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... If Write Pulse ends before MPLX9 Low, use specifications Write Pulse ends after MPLX9 Low, use specifications t 4 This is the earliest time for MPLX9 Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual. / IACK MPLX9 ...

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... Figure 21. IDMA Read, Long Read Cycle (IDMA Mode, Multiplex Bus) REV IKHR t IKR t IRP t t IRDE IKDS PREVIOUS READ DATA DATA t IRDV t IRDH –31– ADSP-2141L Min Max Unit 0.5t – – – ...

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... ADSP-2141L Parameter IDMA Read, Short Read Cycle (IDMA Mode, Multiplex Bus) Timing Requirements: t MPLX9 Low Before Start of Read IKR t Duration of Read IRP Switching Characteristics: t MPLX9 High After Start of Read IKHR t MPLX_BUS Data Hold After End of Read IKDH t MPLX_BUS Data Disabled After End of Read ...

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... CAPACITIVE LOADING Figures 23 and 24 show the capacitive loading characteristics of the ADSP-2141L + 3. 100 150 C – Figure 23. Typical Output Rise Time vs. Load Capacitance, C (at Maximum Ambient Operating Temperature NOMINAL – ...

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... AMB CASE Case Temperature in C CASE OUTPUT DRIVE CURRENTS Figures 28 and 29 show typical I-V characteristics for the output drivers of the ADSP-2141L. The curves represent the current drive capability of the output drivers as a function of output voltage. 100 V = 3. ...

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... MHz = 34 MHz = 19 MHz = 2 MHz = 4 +61 mW. 55 INT –35– ADSP-2141L POWER, INTERNAL 823mW V = 3.6V DD 706mW 649mW V = 3.3V DD 554mW 509mW V = 3.0V DD 431mW FREQUENCY – MHz Figure 30. Power vs. Frequency POWER, IDLE ...

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... ADSP-2141L For all multiplexed pins the active sense is determined by the mode selected. Pin # Pin Name Pin # Pin Name EMS 1 43 PCI_CLK GND 3 GND 45 MPLX_BUS[30] 4 ECLK 46 MPLX_BUS[29] 5 ELOUT 47 MPLX_BUS[28] 6 ELIN 48 MPLX_BUS[27] EINT 7 49 VDD EBR 8 50 GND EBG 9 51 MPLX_BUS[26] 10 MMAP ...

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... MPLX_BUS/Pci_ad[28] 47 MPLX_BUS/Pci_ad[27] 48 VDD 49 GND 50 MPLX_BUS/Pci_ad[26] 51 MPLX_BUS/Pci_ad[25] 52 REV. 0 PINOUT PCI Mode OO ADSP-2141L TOP VIEW (Not to Scale) PCI MODE –37– ADSP-2141L ADDR[25] 156 155 ADDR[24] 154 ADDR[23] 153 ADDR[22] 152 ADDR[21] 151 ADDR[20] 150 VDD 149 ADDR[19] 148 ADDR[18] 147 ADDR[17] 146 ...

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... PCI_CLK 43 GND 44 MPLX_BUS/NC[30] 45 MPLX_BUS/NC[29] 46 MPLX_BUS/NC[28] 47 MPLX_BUS/NC[27] 48 VDD 49 GND 50 MPLX_BUS/NC[26] 51 MPLX_BUS/NC[25] 52 PINOUT 2183-Mode OO ADSP-2141L TOP VIEW (Not to Scale) 2183 MODE –38– ADDR[25] 156 ADDR[24] 155 ADDR[23] 154 ADDR[22] 153 ADDR[21] 152 ADDR[20] 151 VDD 150 ADDR[19] 149 148 ADDR[18] 147 ADDR[17] ...

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... C to +70 C NOTES 1 The ADSP-2141LKS- electrically equivalent, full function, production (non x-grade) version of the product described in this data sheet. (Full function = Triple DES enabled, full 168-bit key length, full 2048-bit public key lengths, red keys allowed.) 2 The ADSP-2141LKS- electrically equivalent, full function, production (non x-grade) version of the product d escribed in this data sheet except for the following: Encryption: DES only, with maximum 56-bit key length ...