CY2213ZC-2 Cypress Semiconductor Corporation., CY2213ZC-2 Datasheet

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CY2213ZC-2

Manufacturer Part Number
CY2213ZC-2
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number:
CY2213ZC-2
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Part Number:
CY2213ZC-2
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CYPRESS/赛普拉斯
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Cypress Semiconductor Corporation
Document #: 38-07263 Rev. *E
1CY2213
Block Diagram
Pin Configuration
• Jitter peak-peak (TYPICAL) = 35 ps
• LVPECL output
• Default Select option
• Serially-configurable multiply ratios
• Output edge-rate control
• 16-pin TSSOP
• High frequency
• 3.3V operation
SER DATA
SER CLK
SER CLK
XOUT
VDDX
VSSX
XOUT
VDD
VSS
Features
XIN
OE
XIN
OE
S
16-pin TSSOP
1
2
3
4
5
6
7
8
CY2213
Oscillator
16
15
14
13
12
11
10
9
Xtal
S
VDD
VSS
CLK
CLKB
VSS
VDD
SER DATA
3901 North First Street
High-accuracy clock generation
One pair of differential output drivers
Phase-locked loop (PLL) multiplier select
Eight-bit feedback counter and six-bit reference counter for high accuracy
Minimize electromagnetic interference (EMI)
Industry-standard, low-cost package saves on board space
125- to 400-MHz (-1) or to 500-MHz (-2) extended output range for high-speed
applications
Enables application compatibility
High-Frequency Programmable PECL
PLL
xM
San Jose
Benefits
,
CA 95134
Clock Generator
Revised May 23, 2003
CLK
CLKB
408-943-2600
CY2213
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CY2213ZC-2 Summary of contents

Page 1

Features • Jitter peak-peak (TYPICAL • LVPECL output • Default Select option • Serially-configurable multiply ratios • Output edge-rate control • 16-pin TSSOP • High frequency • 3.3V operation Block Diagram XIN Xtal Oscillator XOUT OE ...

Page 2

Pin Description Pin Name Pin Number VDDX 1 3.3V Power Supply for Crystal Driver VSSX 2 Ground for Crystal Driver XOUT 3 Reference Crystal Feedback XIN 4 Reference Crystal Input VDD 5 3.3 V Power Supply (all ...

Page 3

clk clk clk vic e S clk S data Start (S) 1 bit 7 bits 1 bit Slave Address R/W S Data ...

Page 4

PLL Frequency = Reference x P/Q = Output Reference Absolute Maximum Conditions The following table reflects stress ratings only, and functional operation at the maximums are not guaranteed. Parameter V Max. voltage on V DD,ABS DD V Max. voltage on ...

Page 5

State Transition Characteristics Specifies the maximum settling time of the CLK and CLKB outputs from device power-up. For V sequences are allowed to power-up and power-down the CY2213. From To Transition Latency CLK/CLKB Normal DD DDX AC ...

Page 6

Functional Specifications Crystal Input The CY2213 receives its reference from an external crystal. Pin XIN is the reference crystal input, and pin XOUT is the reference crystal feedback. The parameters for the crystal are given on page 5 of this ...

Page 7

The PECL differential driver is designed for low-voltage, high-frequency operation. It significantly reduces the transient switching noise and power dissipation when compared to conventional CMOS drivers. The nominal value of the channel impedance The pull-up and pull-down ...

Page 8

Figure 12 shows the definition of cycle-to-cycle duty cycle error. Cycle-to-cycle duty cycle error is defined as the difference between high-times of adjacent cycles over many cycles (typically 12800 cycles at 400 MHz). Equal require- ments apply to the low-times. ...

Page 9

... CY2213ZC-1T 16-lead TSSOP – Tape and Reel Commercial, to 400 MHz CY2213ZC-2 16-lead TSSOP CY2213ZC-2T 16-lead TSSOP – Tape and Reel Commercial, to 500 MHz Package Drawing and Dimensions 16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 CyberClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders ...

Page 10

Document History Page Document Title: CY2213 High-Frequency Programmable PECL Clock Generator Document Number: 38-07263 Orig. of REV. ECN NO. Issue Date Change ** 113090 02/06/02 DSG *A 113512 05/24/02 CKN *B 121882 12/14/02 RBI *C 123215 12/19/02 LJN *D 124012 ...

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