CY2272PVC-1 Cypress Semiconductor Corporation., CY2272PVC-1 Datasheet

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CY2272PVC-1

Manufacturer Part Number
CY2272PVC-1
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Features
Functional Description
The CY2272 is a clock synthesizer/driver for a Pentium, Cyrix
6x86, or AMD K6 processor-based mobile PC using Intel®’s
82430TX, Aladdin IV+ or other similar chipsets.
The CY2272-1 outputs four CPU clocks at 2.5V or 3.3V. There
are seven PCI clocks, running at one half the CPU clock fre-
quency. One of the PCI clocks is free-running. Another leads
Cypress Semiconductor Corporation
CPU_STOP
PCI_STOP
Logic Block Diagram
PWR_DWN
• Mixed 2.5V and 3.3V operation
• Complete clock solution for Pentium®, Cyrix, and AMD
• 1 ns–4 ns delay between CPU and PCI clocks
• I
• Factory-EPROM programmable output drive and slew
• Factory-EPROM programmable CPU clock frequencies
• Dedicated Power-down, CPU stop and PCI stop pins
• Available in space-saving 48-pin SSOP package
Intel and Pentium are registered trademarks of Intel Corporation.
I
2
processor-based motherboards
rate for EMI customization
for custom configurations
XTALOUT
C is a trademark of Philips Corporation.
— Four CPU clocks at 2.5V or 3.3V with three dedicated
— Six 3.3V SDRAM clocks, support three portable
— Seven synchronous PCI clocks, one free-running,
— One 3.3V 48 MHz USB clock
— One 3.3V 24 MHz IO clock
— Two high drive 3.3V Ref. clocks at 14.318 MHz
2
XTALIN
C™ Serial Configuration Interface
SDATA
CPU frequency select inputs
DIMMs
one early
SCLK
SEL0
SEL1
SEL2
Pentium®, 6x86, K6 Clock Synthesizer/Driver for Mobile
PCs with Intel® 82430TX or Ali IV/V+ and 3 SO-DIMMs
14.318
OSC.
MHz
INTERFACE
CONTROL
SERIAL
LOGIC
SYS PLL
EPROM
CPU
PLL
/2 or /2.5
Delay
/2
STOP
LOGIC
3901 North First Street
STOP
LOGIC
the PCI clocks by 1–4 ns. Additionally, the part outputs six 3.3V
SDRAM clocks, one 3.3V USB clock at 48 MHz, one IO clock
at 24 MHz, and two high-drive 3.3V reference clocks at 14.318
MHz.
The part possesses dedicated power-down, CPU stop, and
PCI stop pins for power management control. When the
CPU_STOP input is asserted, the CPU clock outputs are driv-
en LOW. When the PCI_STOP input is asserted, the PCI clock
outputs (except the free-running PCI clock) are driven LOW.
When the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.
The CY2272 outputs are designed for low EMI emissions.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.
CY2272 Selector Guide
Note:
a
1.
V
CPU (13.75, 15, 16.6, 18.75, 55, 60, 66.6, 75 MHz)
SDRAM
PCI (CPU/2MHz)
USB (48MHz)
IO (24MHz)
Ref (14.318MHz)
CPU-PCI delay
EPCICLK
REF [0-1] (14.318 MHz)
CPUCLK [0-3]
SDRAM [0-5]
PCICLK [0-5]
PCICLK_F
DDCPU
USBCLK
IOCLK
One free-running PCI clock, one early PCI clock.
San Jose
Clock Outputs
PWR_DWN
PCICLK_F
XTALOUT
PCICLK1
PCICLK2
PCICLK3
PCICLK4
EPCICLK
PCICLK0
XTALIN
SDATA
V
V
V
REF1
REF0
SCLK
AV
SEL1
DDQ3
DDQ3
DDQ3
Pin Configuration
V
V
V
V
V
CA 95134
DD
SS
SS
SS
SS
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Top View
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
October 12, 1998
408-943-2600
CY2272
V
USBCLK
IOCLK
V
CPUCLK0
CPUCLK1
V
CPUCLK2
CPUCLK3
V
SDRAM0
SDRAM1
V
SDRAM2
SDRAM3
V
SDRAM5
CPU_STOP
PCI_STOP
V
SEL0
SEL2
SDRAM4
V
DDQ3
SS
DDCPU
SS
DDQ3
SS
DDQ3
SS
1–4 ns
7
-1
4
6
1
1
2
[1]

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CY2272PVC-1 Summary of contents

Page 1

Pentium®, 6x86, K6 Clock Synthesizer/Driver for Mobile PCs with Intel® 82430TX or Ali IV/V+ and 3 SO-DIMMs Features • Mixed 2.5V and 3.3V operation • Complete clock solution for Pentium®, Cyrix, and AMD processor-based motherboards — Four CPU clocks at ...

Page 2

Pin Summary Name Pins V 7, 14, 19, 30, 36, 48 DDQ3 V 42 DDCPU 16, 18, 22, 27, 33, 39, 45 Ground SS [2] XTALIN 4 [2] XTALOUT 5 PCI_STOP 28 CPU_STOP 29 ...

Page 3

Actual Clock Frequency Values Target Actual Frequency Frequency Clock Output (MHz) (MHz) CPUCLK 66.67 66.654 CPUCLK 60.0 60.0 CPUCLK 75.0 75.0 USBCLK 48.0 48.008 IOCLK 24.0 24.004 Power Management Logic CPU_STOP PCI_STOP PWR_DWN ...

Page 4

Byte 1: CPU Active/Inactive Register (1 = Active Inactive), Default = Active Bit Pin # Description Bit 7 47 USBCLK (Active/Inactive) Bit 6 46 IOCLK (Active/Inactive) Bit 5 N/A (Reserved) drive to ‘0’ Bit 4 N/A Not used ...

Page 5

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage .............................................. –0. [5] Operating Conditions Parameter Analog and Digital Supply Voltage DD ...

Page 6

Switching Characteristics Parameter Output Description t All Output Duty Cycle 1 t CPUCLK CPU Clock Rising and 2 Falling Edge Rate t REF[0-1] REF Clock Rising and 2 Falling Edge Rate t PCICLK, PCI, EPCI, Clock Rising 2 EPCICLK ...

Page 7

Timing Requirement for the I Parameter t SCLK Clock Frequency 12 t Time the bus must be free before a new transmission can start 13 t Hold time start condition. After this period the first clock pulse is generated. ...

Page 8

Switching Waveforms (continued) CPU-SDRAM Clock Skew CPUCLK SDRAM t 7 CPU-PCI Clock Skew CPUCLK PCICLK t 6 PCI-PCI Clock Skew PCICLK PCICLK t 8 EPCI-PCI Clock Skew EPCICLK PCICLK t 9 [8, 9] CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) ...

Page 9

Switching Waveforms (continued) [10, 11] PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and ...

Page 10

Application Information Clock traces must be terminated with either series or parallel termination, as they are normally done. Application Circuit Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C ...

Page 11

... Test Circuit Note: All Capacitors must be placed as close to the pins as is possible Ordering Information Package Ordering Code Name CY2272PVC–1 O48 Document #: 38–00607–C V DDQ3 1 48 0 0 0 0.1 F OUTPUTS 22 C LOAD Operating ...

Page 12

Package Diagram © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does ...

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