CY2283PVC-1 Cypress Semiconductor Corporation., CY2283PVC-1 Datasheet

CY2283PVC-1

Manufacturer Part Number

CY2283PVC-1

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY2283PVC-1.pdf (12 pages)

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Features

Functional Description

The CY2283 is a clock Synthesizer/Driver for Pentium, Cyrix,

or AMD processor-based PCs using the ALI Aladdin V (-1 op-

tion) or VIA MVP3 (-2 option) chipset.

The CY2283 outputs four CPU clocks at 2.5V or 3.3V. There

are five PCI clocks, running at 30 or 33.3 MHz. One of the PCI

clocks is free-running. Additionally, the part outputs twelve

3.3V SDRAM clocks

one 3.3V reference clock at 14.318 MHz. Finally, the part out-

puts two AGP clocks running at 66.66 MHz or 60 MHz.

The CY2283 has the flexibility to work as either a one-chip or

as part of a two-chip clocking solution. In 100-MHz board de-

signs based on the ALI Aladdin V chipset, it is recommended

that the CY2283 be used with an external SDRAM buffer so-

lution such as the CY2318NZ or CY2314NZ. In this configura-

tion the SDRAM outputs on the CY2283 must be either turned

off using I

Cypress Semiconductor Corporation

Logic Block Diagram

XTALOUT

• Mixed 2.5V and 3.3V operation

• Complete clock solution for Pentium® /II, Cyrix 6x86,

• Support for ALI (-1 option) and VIA (-2 option)

• I

• Full EMI control with factory-EPROM programmable

• Factory-EPROM programmable CPU clock frequencies

• Power-down, CPU stop, and PCI stop pins

• Available in space-saving 48-pin SSOP package

XTALIN

SDATA

and AMD K6 processor-based motherboards

output drive and slew rate

for custom configurations

— Four CPU clocks at 2.5V or 3.3V

— Twelve 3.3V SDRAM clocks

— Five synchronous PCI clocks, one free-running

— One 3.3V 48 MHz USB clock

— One 3.3V Ref. clock at 14.318 MHz

— Two AGP clocks at 3.3V

MODE

SCLK

SEL0

SEL1

C™ Serial Configuration Interface

Pentium®/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for

C or left floating. The CY231xNZ family provides the

Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs

14.318

OSC.

MHz

INTERFACE

CONTROL

SERIAL

LOGIC

[1]

SYS PLL

, one 3.3V USB clock at 48 MHz, and

EPROM

CPU

PLL

Delay (-2 option)

Delay (-1 option)

/1, /1.25, /1.5

[1]

STOP

LOGIC

•

3901 North First Street

STOP

LOGIC

PRELIMINARY

REF0 (14.318 MHz)

CPUCLK [0-3]

SDRAM5/PWR_DWN

SDRAM [0-4],[8-11]

SDRAM6/CPU_STOP

SDRAM7/PCI_STOP

PCICLK_F

USBCLK

DDCPU

AGP

PCI [0-3]

SDRAM outputs in place of the CY2283 and can be placed in

close proximity to the SDRAM modules.

The CY2283 possesses power-down, CPU stop, and PCI stop

pins for power management control. These inputs are multi-

plexed with SDRAM clock outputs, and are selected when the

MODE pin is driven LOW. Additionally, the signals are synchro-

nized on-chip, and ensure glitch-free transitions on the out-

puts. When the CPU_STOP input is asserted, the CPU clock

outputs are driven LOW. When the PCI_STOP input is assert-

ed, the PCI clock outputs (except the free-running PCI clock)

are driven LOW. When the PWR_DWN pin is asserted, the

reference oscillator and PLLs are shut down, and all outputs

are driven LOW.

The CY2283 outputs are designed for low EMI emissions.

Controlled rise and fall times, unique output driver circuits and

factory-EPROM programmable output drive and slew-rate en-

able optimal configurations for EMI control.

CY2283 Selector Guide

Notes:

CPU (66.6, 75, 83.3, 100MHz)

SDRAM

PCI (30, 33.3 MHz)

USB (48MHz)

AGP (66.6, 60MHz)

Ref. (14.318 MHz)

CPU-PCI delay

AGP clock

SDRAM clocks available up to 83.3MHz. In 100-MHz designs based on the

ALI V chipset, an external CY231xNZ buffer should be used.

One free-running PCI clock

•

Clock Outputs

San Jose

Pin Configuration (48 SSOP)

PCICLK_F

SDRAM10

XTALOUT

SDRAM11

PCICLK0

PCICLK2

PCICLK3

SDRAM9

SDRAM8

PCICLK1

XTALIN

SDATA

•

AGP0

AGP1

REF0

SCLK

DDQ3

CA 95134

2.5 5.5 ns

-1 (ALI V)

In phase

with PCI

[2]

[1]

•

October 12, 1998

USBCLK

SEL1

CPUCLK0

CPUCLK1

CPUCLK2

CPUCLK3

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAM5/PWR_DWN

SDRAM6/CPU_STOP

SDRAM7/PCI_STOP

SEL0

MODE

SDRAM4

-2 (VIA MVP3)

DDQ3

DDCPU

DDQ3

408-943-2600

CY2283

2.5 5.5 ns

with CPU

In phase

[2]

Related parts for CY2283PVC-1

CY2283PVC-1 Summary of contents

Page 1

Pentium®/II, K6, 6x86 100-MHz Clock Synthesizer/Driver for Desktop PCs with ALI or VIA Chipsets, AGP and 3 DIMMs Features • Mixed 2.5V and 3.3V operation • Complete clock solution for Pentium® /II, Cyrix 6x86, and AMD K6 processor-based motherboards — ...

Page 2

Pin Summary Name Pins V 6, 14, 19, 30, 36, 48 3.3V Digital voltage supply DDQ3 V 42 DDCPU 16, 22, 27, 33, SS 39, 45 [3] XTALIN 4 [3] XTALOUT 5 SDRAM7/ PCI_STOP ...

Page 3

Actual Clock Frequency Values Target Actual Frequency Frequency Clock Output (MHz) (MHz) CPUCLK 66.67 66.51 CPUCLK 75.0 75.0 CPUCLK 83.33 83.14 CPUCLK 100.0 99.77 USBCLK 48.0 48.01 [4] Power Management Logic - Active when MODE pin is held ‘LOW’ CPU_STOP ...

Page 4

Byte 1: CPU Active/Inactive Register (1 = Active Inactive), Default = Active Bit Pin # Description Bit 7 47 USBCLK Bit 6 N/A (Reserved) drive to ‘0’ Bit 5 N/A (Reserved) drive to ‘0’ Bit 4 N/A Not ...

Page 5

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Supply Voltage ..................................................–0.5 to +7.0V Input Voltage .............................................. –0. [7] Operating Conditions Parameter Analog and Digital Supply Voltage DD ...

Page 6

Switching Characteristics for CY2283-1 Parameter Output Description t All Output Duty Cycle 1 t CPUCLK CPU Clock Rising and 2 Falling Edge Rate t AGP, AGP, REF0 Clock Rising 2 REF0 and Falling Edge Rate t PCI PCI Rising and ...

Page 7

Switching Characteristics for CY2283-2 Parameter Output Description t All Output Duty Cycle 1 t CPUCLK CPU Clock Rising and 2 Falling Edge Rate t SDRAM, SDRAM, AGP, REF0 Clock 2 AGP, REF0 Rising and Falling Edge Rate t PCI PCI ...

Page 8

Switching Waveforms Duty Cycle Timing OUTPUT All Outputs Rise/Fall Time OUTPUT CPU-CPU Clock Skew CPUCLK CPUCLK t 5 CPU-SDRAM Clock Skew CPUCLK SDRAM t 7 CPU-PCI Clock Skew CPUCLK PCICLK t 6 PCI-PCI Clock Skew PCICLK ...

Page 9

Switching Waveforms (continued) AGP-PCI Clock Skew AGPCLK PCICLK t 9 [12, 13] CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) [14, 15] PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN ...

Page 10

Application Circuit Clock traces must be terminated with either series or parallel termination, as they are normally done Summary • A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C this crystal ...

Page 11

... Test Circuit 0.1 F 0.1 F 0.1 F 0.1 F Note: All Capacitors must be placed as close to the pins as is possible Ordering Information Package Ordering Code Name CY2283PVC–1 O48 CY2283PVC–2 O48 Document #: 38–00685–A Intel and Pentium are registered trademarks of Intel Corporation. I PRELIMINARY V DDQ3 ...

Page 12

Package Diagram © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does ...

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