CY2SSTV8575AC Cypress Semiconductor Corporation., CY2SSTV8575AC Datasheet

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CY2SSTV8575AC

Manufacturer Part Number
CY2SSTV8575AC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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CY2SSTV8575AC
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4 909
TV8575
Features
Cypress Semiconductor Corporation
Document #: 38-07458 Rev. **
• Operating frequency: 60 MHz to 170 MHz
• Supports 266-MHz DDR SDRAM
• 5 differential outputs from 1 differential input
• Spread Spectrum compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power Management Control input
• High-impedance outputs when input clock < 20 MHz
• 2.5V operation
• 32-pin TQFP JEDEC MS-026 C
Block Diagram
AVDD
CLK
CLK#
FBIN
OE
FBI
N
#
23
8
21
22
5
6
Powerdown
Test and
PLL
Logic
16
18
19
12
11
15
27
28
30
31
2
1
Y0
Y0#
Y1
Y1#
Y2
Y2#
Y3
Y3#
Y4
Y4#
FBOUT#
FBOUT
3901 North First Street
Description
The CY2SSTV8575 is a high-performance, low-skew, low jitter
zero-delay buffer designed to distribute differential clocks in
high-speed applications. The CY2SSTV8575 generates five
differential pair clock outputs from one differential pair clock
input. In addition, the CY2SSTV8575 features differential
feedback clock outputs and inputs. This allows the
CY2SSTV8575 to be used as a zero-delay buffer.
When used as a zero-delay buffer in nested clock trees, the
CY2SSTV8575 locks onto the input reference and translates
with near zero delay to low-skew outputs.
VDDQ
VDDQ
VSS
VSS
Y3#
Y4#
Y4
Y3
Pin Configuration
Differential Clock Buffer/Driver
24 23 22 21 20 19 18 17
San Jose
1 2 3 4 5 6 7 8
CY2SSTV8575
JEDEC MS-026 C
TQFP-32
CA 95134
CY2SSTV8575
Revised October 30, 2002
AVSS
Y2#
Y1#
VSS
Y2
VSS
VDDQ
Y1
408-943-2600
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CY2SSTV8575AC Summary of contents

Page 1

TV8575 Features • Operating frequency: 60 MHz to 170 MHz • Supports 266-MHz DDR SDRAM • 5 differential outputs from 1 differential input • Spread Spectrum compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps ...

Page 2

Pin Description Pin Name I/O 5,6 CLK, CLK Differential Input 21 FBIN# I Differential Input 22 FBIN I 2,12,15,27,30 Y(0:4) O Differential Outputs 1,11,16,28,31 Y(0:4 FBOUT O Differential Outputs 19 FBOUT 3,4,7,13,20,26, ...

Page 3

Power Management Functions Output enable/disable control of the CY2SSTV8575 allows the user to implement power management schemes into the de- sign. Outputs are three-stated/disabled when OE is asserted low, see Table 1. The enabling and disabling of outputs is done ...

Page 4

DDR-SDRAM represents a capacitive load CLK 120 Ohm CLK# 120 Ohm VDD VDD Figure 3. Differential Signal Using Direct Termination Resistor Governing Agencies The following agencies provide specifications that apply to the CY2SSTV8575. ...

Page 5

Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any volt- age higher than the maximum rated voltages to ...

Page 6

AC Input Parameters (AV = VDDQ = 2.5 ±5 Parameter Description F Input Frequency in D Input Duty Cycle TYC AC Output Parameters (AVDD= VDDQ = 2.5 ±5%, Temperature = 0°C to +85°C) Parameter Description F Output frequency ...

Page 7

... Ordering Information Part Number CY2SSTV8575AC 32-pin TQFP CY2SSTV8575ACT 32-pin TQFP -Tape & Reel Package Drawing and Dimension 32-Lead Thin Plastic Quad Flatpack 1.0 mm A32 All product and company names mentioned in this document may be the trademarks of their respective owners. Document #: 38-07458 Rev. ** © ...

Page 8

Document History Page Document Title: CY2SSTV8575 Differential Clock Buffer/Driver Document #: 38-07458 Issue Rev. ECN No. Date ** 120711 10/31/02 Document #: 38-07458 Rev. ** Orig. of Change Description of Change RGL New Data Sheet CY2SSTV8575 Page ...

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