CY62158DV30LL-55ZSXI Cypress Semiconductor Corporation., CY62158DV30LL-55ZSXI Datasheet

no-image

CY62158DV30LL-55ZSXI

Manufacturer Part Number
CY62158DV30LL-55ZSXI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05391 Rev. *D
Features
Functional Description
The CY62158DV30 is a high-performance CMOS static RAMs
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
Note:
• Very high speed: 45 ns, 55 ns and 70 ns
• Ultra-low active power
• Ultra-low standby power
• Easy memory expansion with CE
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball BGA, 48-pin TSOPI, and
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.
— Wide voltage range: 2.20V – 3.60V
— Typical active current:1.5 mA @ f = 1 MHz
— Typical active current: 12 mA @ f = f
features
44-pin TSOPII
CE
CE
1
2
[1]
WE
OE
A
A
A
A
A
A
A
A
A
A
A
A
A
11
12
10
1
2
9
0
3
4
5
7
8
6
1
, CE
2
max
, and OE
3901 North First Street
Data in Drivers
8-Mbit (1024K x 8) MoBL
1024K x 8
DECODER
ARRAY
COLUMN
POWER
DOWN
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption by 85% when
deselected (CE
Writing to the device is accomplished by taking Chip Enable 1
(CE
(CE
then written into the location specified on the address pins (A
through A
Reading from the device is accomplished by taking Chip
Enable 1 (CE
Enable 2 (CE
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
LOW and CE
during a write operation (CE
LOW). See the truth table for a complete description of read
and write modes.
1
2
) and Write Enable (WE) inputs LOW and Chip Enable 2
) HIGH. Data on the eight I/O pins (I/O
19
).
2
2
) HIGH while forcing Write Enable (WE) HIGH.
1
HIGH), the outputs are disabled (OE HIGH), or
San Jose
1
) and Output Enable (OE) LOW and Chip
HIGH or CE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
,
CA 95134
0
1
2
3
4
5
6
7
2
1
LOW).
LOW and CE
0
through I/O
Revised June 17, 2004
CY62158DV30
Static RAM
0
7
2
) are placed in a
through I/O
HIGH and WE
408-943-2600
MoBL
7
) in
) is
0
1
[+] Feedback

Related parts for CY62158DV30LL-55ZSXI

CY62158DV30LL-55ZSXI Summary of contents

Page 1

Features • Very high speed and 70 ns — Wide voltage range: 2.20V – 3.60V • Ultra-low active power — Typical active current:1 MHz — Typical active current ...

Page 2

Pin Configuration A 48TSOPI A Top View A15 1 A14 2 A13 3 A12 4 A11 5 A10 DNU DNU 13 DNU 14 DNU ...

Page 3

... Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V Document #: 38-05391 Rev. *D Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range + 0.3V cc(max) Product CY62158DV30L + 0.3V CC(max) CY62158DV30LL + 0.3V CC(max) Operating MHz Speed [8] Max. (ns) Typ. Max. 3.6 45,55,70 1 ...

Page 4

Capacitance Parameter Description C Input Capacitance IN C Output Capacitance OUT Thermal Resistance Parameter Description [9] Θ Thermal Resistance Still Air, soldered 4.5 inch, four-layer JA (Junction to Ambient) printed circuit board [9] Θ ...

Page 5

Data Retention Waveform Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE ...

Page 6

Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [18, 19] Read Cycle No. 2 (OE Controlled) ADDRESS ACE OE t LZOE HIGH IMPEDANCE DATA OUT t LZCE t ...

Page 7

Switching Waveforms (continued) Write Cycle No. 2( Controlled ADDRESS DATA I/O Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS [21] NOTE ...

Page 8

... Ordering Code 45 CY62158DV30L-45BVI CY62158DV30LL-45BVI 45 CY62158DV30L-45ZXI CY62158DV30LL-45ZXI 45 CY62158DV30L-45ZSXI CY62158DV30LL-45ZSXI 55 CY62158DV30L-55BVI CY62158DV30LL-55BVI 55 CY62158DV30L-55ZXI CY62158DV30LL-55ZXI 55 CY62158DV30L-55ZSXI CY62158DV30LL-55ZSXI 70 CY62158DV30L-70BVI CY62158DV30LL-70BVI 70 CY62158DV30L-70ZXI CY62158DV30LL-70ZXI 70 CY62158DV30L-70ZSXI CY62158DV30LL-70ZSXI Document #: 38-05391 Rev. *D Package Name Package Type BV48A 48-ball Fine Pitch BGA (6 mm × 8mm × 1 mm) Z-48 48 Pin TSOP I (Pb-free) ZS-44 ...

Page 9

Package Diagrams 48-Lead TSOP 1.0 mm) Z48A DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 1 0.004[0.10] 0.008[0.21] 0°-5° Document #: 38-05391 Rev. *D 48-lead VFBGA ( mm) BV48A ...

Page 10

Package Diagrams (continued) MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-05391 Rev. *D © Cypress ...

Page 11

Document History Page  Document Title:CY62158DV30 MoBL Document Number: 38-05391 Orig. of REV. ECN NO. Issue Date Change ** 126293 05/22/03 HRT *A 131014 11/25/03 CBD *B 133114 01/24/04 CBD *C 211602 See ECN AJU *D 239450 See ECN SYT/AJU ...

Related keywords