CY7C1006B-15VI Cypress Semiconductor Corporation., CY7C1006B-15VI Datasheet

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CY7C1006B-15VI

Manufacturer Part Number
CY7C1006B-15VI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05037 Rev. **
Features
Functional Description
The CY7C106B and CY7C1006B are high-performance
CMOS static RAMs organized as 262,144 words by 4 bits.
Easy memory expansion is provided by an active LOW Chip
Selection Guide
• High speed
• CMOS for optimum speed/power
• Low active power
• Low standby power
• 2.0V data retention (optional)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
Logic Block Diagram
— t
— 495 mW
— 275 mW
— 100 W
A
A
A
A
A
A
A
A
A
AA
1
2
3
4
5
6
7
8
9
= 12 ns
INPUT BUFFER
512 x 512 x 4
DECODER
ARRAY
COLUMN
7C1006B-12
7C106B-12
12
90
50
POWER
DOWN
3901 North First Street
7C1006B-15
7C106B-15
15
80
30
Enable (CE), an active LOW Output Enable (OE), and
three-state drivers. These devices have an automatic pow-
er-down feature that reduces power consumption by more
than 65% when the devices are deselected.
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the four I/O
pins (I/O
fied on the address pins (A
Reading from the devices is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the four I/O pins.
The four input/output pins (I/O
high-impedance state when the devices are deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE and WE LOW).
The CY7C106B is available in a standard 400-mil-wide SOJ;
the CY7C1006B is available in a standard 300-mil-wide SOJ.
C106B–1
I/O
I/O
I/O
I/O
WE
CE
OE
7C1006B-20
3
2
1
0
7C106B-20
0
through I/O
San Jose
20
75
30
256K x 4 Static RAM
3
Pin Configuration
GND
) is then written into the location speci-
A
CE
OE
A
A
A
A
A
A
A
A
A
A
10
7C1006B-25
0
1
2
3
4
5
6
7
8
9
7C106B-25
0
through A
CA 95134
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
0
25
70
30
SOJ
through I/O
Revised August 24, 2001
28
27
26
25
24
23
22
21
20
19
18
17
16
15
17
C106B–2
CY7C1006B
).
V
A
A
A
A
A
A
A
NC
I/O
I/O
I/O
I/O
WE
CY7C106B
CC
17
16
15
14
13
12
11
1
3
2
0
3
) are placed in a
7C106B-35
408-943-2600
35
60
25

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CY7C1006B-15VI Summary of contents

Page 1

... I/O pins. The four input/output pins (I/O high-impedance state when the devices are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C106B is available in a standard 400-mil-wide SOJ; the CY7C1006B is available in a standard 300-mil-wide SOJ. I/O 3 I/O 2 I/O 1 ...

Page 2

... DC Input Voltage .................................–0. Document #: 38-05037 Rev. ** Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range [1] .... –0.5V to +7.0V Range + 0.5V Commercial CC Industrial + 0.5V CC CY7C106B CY7C1006B Ambient [2] Temperature + 10% – +85 C Page ...

Page 3

... Max > > < MAX Max Com’ > V – 0.3V > V – 0. < 0.3V CY7C106B CY7C1006B 7C106B-12 7C106B-15 7C106B-20 7C1006B-15 7C1006B-20 Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2.2 V 2 +0.3 +0.3 0.8 –0.3 0.8 –0.3 –1 +1 –1 +1 – ...

Page 4

... Document #: 38-05037 Rev. ** Test Conditions MHz 5. 480 3. GND 5 pF 255 INCLUDING Rise Time < 1V/ns JIG AND SCOPE (b) C106B–3 1.73V CY7C106B CY7C1006B Max. Unit ALL INPUT PULSES 90% 90% 10% 10% Fall Time < 1V/ns C106B–4 Page ...

Page 5

... HZCE LZCE HZOE LZOE and t HZWE CY7C106B CY7C1006B 7C106B-25 7C1006B-25 7C106B-35 Max. Min. Max. Min. Max. Unit ...

Page 6

... CC CE > > < 0.3V IN DATA RETENTION MODE 4.5V V > CDR OHA ACE t DOE t LZOE 50 CY7C106B CY7C1006B [10] Conditions Min. Max. 2 2.0V, 250 DR – 0.3V – 0. 200 4. DATA VALID t HZOE t HZCE DATA VALID t PD 50% Unit C106B–5 C106B– ...

Page 7

... If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. Data I/O is high impedance Document #: 38-05037 Rev SCE PWE t SD DATA VALID [14, 15 SCE PWE t SD DATA VALID CY7C106B CY7C1006B C106B– C106B–9 Page ...

Page 8

... X X High Data Out Data High Z Ordering Information Speed (ns) Ordering Code 12 CY7C106B-12VC CY7C1006B-12VC 15 CY7C106B-15VC CY7C1006B-15VC CY7C106B-15VI CY7C1006B-15VI 20 CY7C106B-20VC CY7C1006B-20VC CY7C106B-20VI CY7C1006B-20VI 25 CY7C106B-25VC CY7C1006B-25VC CY7C106B-25VI CY7C1006B-25VI 35 CY7C106B-35VC CY7C106B-35VI Document #: 38-05037 Rev. ** [9, 15 SCE PWE t SD ...

Page 9

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded SOJ V21 28-Lead (400-Mil) Molded SOJ V28 CY7C106B CY7C1006B 51-85031-B 51-85032-A Page ...

Page 10

... Document Title: CY7C106B, CY7C1006B 256K x 4 Static RAM Document Number: 38-05037 Issue REV. ECN NO. Date ** 106831 09/17/01 Document #: 38-05037 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00955 to 38-05037 CY7C106B CY7C1006B Page ...

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