CY7C1009L-15VC Cypress Semiconductor Corporation., CY7C1009L-15VC Datasheet

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CY7C1009L-15VC

Manufacturer Part Number
CY7C1009L-15VC
Description
128K x 8 Static RAM, TTL-compatible, 15ns
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-05032 Rev. **
Features
Functional Description
The CY7C109 / CY7C1009 is a high-performance CMOS stat-
ic RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW chip enable (CE
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Maximum CMOS Standby Current (mA)
Low Power Version
Shaded areas contain preliminary information.
• High speed
• Low active power
• Low CMOS standby power
• 2.0V Data Retention (Low power version)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
CE
CE
WE
OE
Logic Block Diagram
— t
— 1017 mW (max., 12 ns)
— 55 mW (max.), 4 mW (Low power version)
1
2
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
AA
= 10 ns
INPUT BUFFER
512 x 256 x 8
DECODER
COLUMN
ARRAY
1
POWER
DOWN
, CE
2
, and OE options
7C1009-10
7C109-10
3901 North First Street
195
10
10
2
1
), an
7C1009-12
7C109-12
185
12
10
109–1
2
active HIGH chip enable (CE
(OE), and three-state drivers. Writing to the device is accom-
plished by taking chip enable one (CE
inputs LOW and chip enable two (CE
the eight I/O pins (I/O
location specified on the address pins (A
Reading from the device is accomplished by taking chip en-
able one (CE
write enable (WE) and chip enable two (CE
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH or CE
during a write operation (CE
The CY7C109 is available in standard 400-mil-wide SOJ and
32-pin TSOP type I packages. The CY7C1009 is available in
a 300-mil-wide SOJ package. The CY7C1009 and CY7C109
are functionally equivalent in all other respects.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
CE
V
A
A
WE
A
A
A
A
NC
CC
A
A
A
A
A
A
11
13
15
16
14
12
7C1009-15
9
8
2
7
6
5
4
7C109-15
155
15
10
San Jose
2
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
LOW), the outputs are disabled (OE HIGH), or
) and output enable (OE) LOW while forcing
128K x 8 Static RAM
7C1009-20
7C109-20
Pin Configurations
0
GND
I/O
I/O
I/O
through I/O
A
A
A
140
NC
A
A
A
A
A
A
A
20
10
A
16
14
12
7
6
5
4
3
2
1
0
0
1
2
(not to scale)
1
CA 95134
Top View
2
LOW, CE
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
), an active LOW output enable
0
SOJ
through I/O
7C1009-25
7C109-25
Revised August 24, 2001
7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
) is then written into the
1
2
) and write enable (WE)
135
2
25
10
) input HIGH. Data on
HIGH, and WE LOW).
CE
A
CE
I/O
I/O
I/O
I/O
I/O
V
A
WE
A
A
A
OE
A
0
10
CC
15
13
8
9
11
7
6
5
4
3
2
1
CY7C1009
through A
109–2
7
CY7C109
) are placed in a
2
) HIGH. Under
408-943-2600
7C1009-35
7C109-35
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
125
35
10
).
109–3
OE
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
10
0
1
2
3
7
6
5
4
3
2
1
0
1

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CY7C1009L-15VC Summary of contents

Page 1

Features • High speed — • Low active power — 1017 mW (max., 12 ns) • Low CMOS standby power — (max.), 4 mW (Low power version) • 2.0V Data Retention (Low power ...

Page 2

Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. – +150 C Ambient Temperature with Power Applied............................................. – +125 C Supply Voltage Relative ...

Page 3

Electrical Characteristics Over the Operating Range (continued) Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH [1] V Input LOW Voltage IL I Input Load Current IX I Output Leakage OZ Current ...

Page 4

Switching Characteristics Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid, CE ACE 1 Valid t OE LOW to ...

Page 5

Switching Characteristics Parameter Description READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid, CE ACE 1 Valid t OE LOW to ...

Page 6

Data Retention Waveform Switching Waveforms [10, 11] Read Cycle No. 1 ADDRESS DATA OUT PREVIOUS DATA VALID [11, 12] Read Cycle No. 2 (OE Controlled) ADDRESS HIGH IMPEDANCE DATA OUT t LZCE ...

Page 7

Switching Waveforms (continued) Write Cycle No Controlled ADDRESS DATA I/O Write Cycle No. 2 (WE Controlled, OE HIGH During Write) ADDRESS ...

Page 8

Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS NOTE 15 DATA I/O Note: 15. During this period the I/Os are in the output state and input signals should not ...

Page 9

... Ordering Information Speed (ns) Ordering Code 10 CY7C109-10VC CY7C1009-10VC CY7C1009L-10VC 12 CY7C109-12VC CY7C1009-12VC CY7C1009L-12VC CY7C109-12ZC 15 CY7C109–15VC CY7C1009-15VC CY7C1009L-15VC CY7C109–15ZC 20 CY7C109–20VC CY7C1009-20VC CY7C109–20VI CY7C109–20ZC CY7C109-20ZI 25 CY7C109–25VC CY7C1009-25VC CY7C109–25VI CY7C109–25ZC CY7C109-25ZI 35 CY7C109–35VC CY7C1009-35VC CY7C109–35VI Shaded areas contain preliminary information. ...

Page 10

Package Diagrams Document #: 38-05032 Rev. ** 32-Lead (300-Mil) Molded SOJ V32 32-Lead (400-Mil) Molded SOJ V33 CY7C109 CY7C1009 51-85041-A 51-85033-A Page ...

Page 11

Package Diagrams (continued) Document #: 38-05032 Rev. ** © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in ...

Page 12

Document Title: CY7C109, CY7C1009 128K x 8 Static RAM Document Number: 38-05032 Issue REV. ECN NO. Date ** 106826 09/15/01 Document #: 38-05032 Rev. ** Orig. of Change Description of Change SZV Change from Spec number: 38-00140 to 38-05032 CY7C109 ...

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