CY7C1342-35JI Cypress Semiconductor Corporation., CY7C1342-35JI Datasheet
CY7C1342-35JI
Related parts for CY7C1342-35JI
CY7C1342-35JI Summary of contents
Page 1
... Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin (CY7C1342 only). The CY7C135 and CY7C1342 are available in 52-pin PLCC. I/O I/O ...
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... L R SEM SEM Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three L R (CY7C1342 only) (CY7C1342 only) least significant bits of the address lines will determine which semaphore to write or read. The I into the respective location. Document #: 38-06038 Rev. *C 7C135-15 ...
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... One Port CE or Com’l L ≥ – 0.2V Ind. ≥V V – 0. ≤ 0.2V Active Port Outputs, [ MAX CY7C135 CY7C1342 Ambient Temperature V CC ° ° + ± 10% ° ° – + ± 10% 7C135-20 7C135-25 7C1342-20 7C1342-25 Unit 2.4 2 ...
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... MHz 5. 250Ω TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND ≤ ≤ CY7C135 CY7C1342 7C135-35 7C135-55 7C1342-35 7C1342-55 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 V 2.2 2.2 V 0.8 0.8 V µA –10 +10 –10 +10 µ ...
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... Test conditions used are Load 3. 8. This parameter is guaranteed but not tested. 9. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. 10. Semaphore timing applies only to CY7C1342. Document #: 38-06038 Rev. *C [5] ...
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... Address valid prior to or coincident with CE transition LOW. 14 =LOW; R/W = HIGH Document #: 38-06038 Rev. *C Either Port Address Access Either Port CE/OE Access t ACE t DOE DATA VALID t wc MATCH t PWE t SD VALID MATCH t WDD . IL CY7C135 CY7C1342 DATA VALID t HZCE t HZOE DDD VALID Page [+] Feedback ...
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... AW t PWE t SD DATA VALID HZOE HIGH IMPEDANCE [16, 18 SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE or (t PWE CY7C135 CY7C1342 LZOE LZWE + allow the I/O drivers to turn off and data to HZWE SD Page [+] Feedback ...
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... Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side (CY7C1342 only) A – VALID ADDRESS t AW SEM I R/W OE Timing Diagram of Semaphore Contention (CY7C1342 only) A – R/W L SEM L A – R/W R SEM R Notes: 19 HIGH for the duration of the above timing (both write and read cycle). ...
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... When reading the device, the user must assert both the OE and CE pins. Data will be available t ACE OE are asserted. If the user of the CY7C1342 wishes to access a semaphore, the SEM pin must be asserted instead of the CE pin. Required inputs for read operations are summa- rized in Table 1. ...
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... AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 20.0 15.0 10 4. 25° 200 400 600 800 1000 CAPACITANCE (pF) CY7C135 CY7C1342 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 140 120 100 5. 25° 1.0 2.0 3.0 4.0 5.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs ...
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... CY7C1342–25JC CY7C1342–25JI 35 CY7C1342–35JC CY7C1342–35JI 55 CY7C1342–55JC CY7C1342–55JI Package Diagrams 52-Lead Plastic Leaded Chip Carrier J69 52-Lead Pb-Free Plastic Leaded Chip Carrier J69 All products and company names mentioned in this document may be the trademarks of their respective holders. ...
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... Document History Page Document Title: CY7C135/CY7C1342 Dual Port Static RAM and Dual Port Static RAM w/Semaphores Document Number: 38-06038 Issue Orig. of REV. ECN NO. Date Change ** 110181 10/21/01 *A 122288 12/27/02 *B 236763 SEE ECN *C 393413 See ECN Document #: 38-06038 Rev. *C Description of Change SZV ...