CY7C135-20JC Cypress Semiconductor Corporation., CY7C135-20JC Datasheet
CY7C135-20JC
Related parts for CY7C135-20JC
CY7C135-20JC Summary of contents
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... Dual-Port Static RAM and Dual-Port SRAM with Semaphores Functional Description The CY7C135 and CY7C1342 are high-speed CMOS dual-port static RAMs. The CY7C1342 includes semaphores that provide a means to allocate portions of the dual-port RAM or any shared resource. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory ...
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... I Description pin is used when writing to a semaphore. Semaphores are requested by writing 0 CY7C135 CY7C1342 7C135-35 7C135-55 7C1342-35 7C1342-55 Unit 160 160 Page [+] Feedback ...
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... One Port CE or Com’l L ≥ – 0.2V Ind. ≥V V – 0. ≤ 0.2V Active Port Outputs, [ MAX CY7C135 CY7C1342 Ambient Temperature V CC ° ° + ± 10% ° ° – + ± 10% 7C135-20 7C135-25 7C1342-20 7C1342-25 Unit 2 ...
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... MHz 5. 250Ω TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND ≤ ≤ CY7C135 CY7C1342 7C135-35 7C135-55 7C1342-35 7C1342-55 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0.4 V 2.2 2.2 V 0.8 0.8 V µA –10 +10 –10 +10 µ ...
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... HZCE LZCE HZOE CY7C135 CY7C1342 7C135-35 7C135-55 7C1342-35 7C1342-55 Unit ...
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... Address valid prior to or coincident with CE transition LOW. 14 =LOW; R/W = HIGH Document #: 38-06038 Rev. *C Either Port Address Access Either Port CE/OE Access t ACE t DOE DATA VALID t wc MATCH t PWE t SD VALID MATCH t WDD . IL CY7C135 CY7C1342 DATA VALID t HZCE t HZOE DDD VALID Page [+] Feedback ...
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... AW t PWE t SD DATA VALID HZOE HIGH IMPEDANCE [16, 18 SCE PWE t SD DATA VALID t HZWE HIGH IMPEDANCE or (t PWE CY7C135 CY7C1342 LZOE LZWE + allow the I/O drivers to turn off and data to HZWE SD Page [+] Feedback ...
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... SPS Document #: 38-06038 Rev. *C [19 VALID ADDRESS SCE t SOP t SD DATA VALID PWE t t SWRD DOE t SOP WRITE CYCLE READ CYCLE [20, 21, 22] MATCH t SPS MATCH = CE = HIGH. L CY7C135 CY7C1342 t OHA t ACE DATA VALID OUT Page [+] Feedback ...
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... Architecture The CY7C135 consists of an array of 4K words of 8 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). Two semaphore control pins exist for the CY7C1342 (SEM ). L/R Functional Description Write Operation Data must be set up for a duration of t before the rising edge SD of R/W in order to guarantee a valid write ...
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... AMBIENT TEMPERATURE (°C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 20.0 15.0 10 4. 25° 200 400 600 800 1000 CAPACITANCE (pF) CY7C135 CY7C1342 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 140 120 100 5. 25° 1.0 2.0 3.0 4.0 5.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs ...
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... Ordering Information 4K x8 Dual-Port SRAM Speed (ns) Ordering Code 15 CY7C135–15JC CY7C135-15JXC 20 CY7C135–20JC 25 CY7C135–25JC CY7C135-25JXC CY7C135–25JI 35 CY7C135–35JC CY7C135–35JI 55 CY7C135–55JC CY7C135–55JI 4K x8 Dual-Port SRAM with Semaphores Speed (ns) Ordering Code 15 CY7C1342–15JC 20 CY7C1342–20JC 25 CY7C1342–25JC CY7C1342–25JI 35 CY7C1342– ...
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... Document History Page Document Title: CY7C135/CY7C1342 Dual Port Static RAM and Dual Port Static RAM w/Semaphores Document Number: 38-06038 Issue Orig. of REV. ECN NO. Date Change ** 110181 10/21/01 *A 122288 12/27/02 *B 236763 SEE ECN *C 393413 See ECN Document #: 38-06038 Rev. *C Description of Change SZV ...