CY7C139AV-25JC Cypress Semiconductor Corporation., CY7C139AV-25JC Datasheet
CY7C139AV-25JC
Related parts for CY7C139AV-25JC
CY7C139AV-25JC Summary of contents
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... CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM Features • True Dual-Ported memory cells which allow simultaneous access of the same memory location • 4K/8K/16K/32K x 8 organizations (CY7C0138AV/144AV/006AV/007AV) • 4K/8K/16K/32K x 9 organizations (CY7C0139AV/145AV/016AV/017AV) • 0.35-micron CMOS for optimum speed/power • ...
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... PLCC Top View CY7C138AV ( CY7C139AV ( 2728 29 30 3132 68-Pin PLCC Top View ...
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... PLCC Top View CY7C006AV (16K CY7C007AV (32K CY7C016AV (16K CY7C017AV (32K CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV INT L BUSY L GND M/S BUSY R INT ...
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... CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -20 20 120 35 10 µA CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV INT L BUSY L GND M/S BUSY R INT CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -25 25 115 30 10 µA Page [+] Feedback ...
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... GND Ground NC No Connect Architecture The CY7C138AV/144AV/006AV/007AV and CY7C139AV/ 145AV/016AV/017AV consist of an array of 4K, 8K, 16K, and 32K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory ...
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... The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C138AV/144AV/006AV/007AV and CY7C139AV/ 145AV/016AV/017AV provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within ...
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... MHz 3.3V CC CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Ambient Temperature V CC ° ° 3.3V ± 300 +70 C ° ° 3.3V ± 300 mV – +85 C CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV -25 Max. Min. Typ. Max. Unit 2.4 V 0.4 0.4 V 2.0 V 0.8 0.8 V µA 10 –10 10 175 115 165 mA 195 mA ...
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... HZCE LZCE HZOE CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 3. 590Ω OUTPUT 435Ω (c) Three-State Delay (Load 2) (Used for & HZWE LZWE including scope and jig) -25 Max. Min. ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C0138AV/144AV/006AV/007AV CY7C139AV/145AV/016AV/017AV are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, ...
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... To access semaphore Document #: 38-06051 Rev. *C [24, 25, 26 DATA VALID [24, 27, 28] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE , SEM = CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV t OHA t HZCE t HZOE DATA VALID OHA t HZCE Page [+] Feedback ...
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... AW [32] t PWE [33] t HZWE t SD [29, 30, 31, 36 SCE LOW CE or SEM PWE CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV [33] t HZOE LZWE Note allow the I/O drivers to turn off and data HZWE SD Page [+] Feedback ...
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... Document #: 38-06051 Rev. *C [37] t SAA VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [38, 39, 40] MATCH t SPS MATCH = CE = HIGH CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV t OHA t ACE DATA VALID OUT t DOE Page [+] Feedback ...
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... Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 41 LOW Document #: 38-06051 Rev. *C CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV [41 MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C007AV/017AV BHA ...
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... BUSY will be asserted. PS Document #: 38-06051 Rev. *C [42] ADDRESS MATCH BLC ADDRESS MATCH BLC [42 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV t BHC t BHC Page [+] Feedback ...
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... INS INR L Document #: 38-06051 Rev [43 (See Functional Description) [44] t INR t WC [43 (See Functional Description) [44] t INR ) is deasserted first R asserted last. L CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV t RC READ FFF t RC READ FFE Page [+] Feedback ...
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... Left port obtains semaphore token 1 1 Semaphore free 1 0 Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV Operation Right Port INT 0R–14R [45 ...
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... Thin Quad Flat Pack J81 68-Pin Plastic Leaded Chip Carrier A65 64-Pin Thin Quad Flat Pack A65 64-Pin Pb-Free Thin Quad Flat Pack J81 68-Pin Plastic Leaded Chip Carrier CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 64-Pin TQFP X X Operating Range Commercial Commercial Operating ...
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... CY7C007AV–25JC 32K x9 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code 20 CY7C017AV–20JC CY7C017AV–20JI 25 CY7C017AV–25JC Document #: 38-06051 Rev. *C CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV Package Name Package Type J81 68-Pin Plastic Leaded Chip Carrier J81 68-Pin Plastic Leaded Chip Carrier Package Name Package Type J81 ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 68-Lead Plastic Leaded Chip Carrier J81 CY7C138AV/144AV/006AV CY7C139AV/145AV/016AV CY7C007AV/017AV 51-85046-*B 51-85005-*A ...
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... Document History Page Document Title: CY7C138AV/144AV/006AV/CY7C139AV/145AV/016AV/CY7C007AV/017AV 3.3V 4K/8K/16K/32K x 8/9 Dual Port SRAM Document Number: 38-06051 Issue Orig. of REV. ECN NO. Date Change ** 110203 12/02/01 SZV *A 122301 12/27/02 *B 237623 See ECN YDT *C 373615 See ECN PCX Document #: 38-06051 Rev. *C Description of Change Change from Spec number: 38-00837 to 38-06051 ...