CY7C1370CV25-167BZC Cypress Semiconductor Corporation., CY7C1370CV25-167BZC Datasheet
CY7C1370CV25-167BZC
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CY7C1370CV25-167BZC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-05235 Rev. *C 512K x 36/ Pipelined SRAM Functional Description The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states ...
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... DQs DQP DQP INPUT INPUT E E REGISTER 0 CY7C1370CV25-200 CY7C1370CV25-167 CY7C1372CV25-200 CY7C1372CV25-167 Unit 3.0 3.4 300 275 Page ...
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... DQa DQb 23 58 DQa DQPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DQPa CY7C1370CV25 CY7C1372CV25 DDQ DQPa 74 DQa 73 DQa DDQ DQa 69 DQa ...
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... F V DDQ DDQ DDQ E(72 DDQ Document #: 38-05235 Rev. *C 119-ball BGA Pinout CY7C1370CV25 (512K × 36) – 14 × 22 BGA ADV/ DQP ...
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... V b DDQ DDQ DDQ N DQP DDQ P NC E(72 MODE E(36) A Document #: 38-05235 Rev. *C 165-Ball fBGA Pinout CY7C1370CV25 (512K × 36) – 13 × 15 fBGA CLK ...
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... TCK. Clock input to the JTAG circuitry. Power supply inputs to the core of the device. Ground for the device. Should be connected to ground of the system. No connects. This pin is not connected to the die. Can either be left unconnected or connected to V CY7C1370CV25 CY7C1372CV25 controls DQ and DQP , BW controls ...
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... ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating. Burst Read Accesses The CY7C1370CV25 and CY7C1372CV25 have an on-chip CY7C1372CV25 are burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs ...
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... CY7C1372CV25) are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1370CV25/CY7C1372CV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above ...
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... Write Both Bytes IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370CV25/CY7C1372CV25 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149 ...
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... TDI and TDO pins when the TAP controller Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the TAP controller is not fully 1149.1-compliant. CY7C1370CV25 CY7C1372CV25 Page ...
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... CK and CK# captured in the boundary scan register. Document #: 38-05235 Rev. *C CY7C1370CV25 CY7C1372CV25 Once the data is captured possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins ...
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... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05235 Rev. *C [9] SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE- EXIT2-DR 1 UPDATE- CY7C1370CV25 CY7C1372CV25 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 ...
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... GND ≤ V ≤ DDQ GND ≤ V ≤ DDQ [12, 13] Over the Operating Range Description (AC) > −0.5V for t < t /2; undershoot: V /2. IL TCYC / ns CY7C1370CV25 CY7C1372CV25 0 Selection 0 Circuitry 0 0 Min. Max. = 2.5V 1.7 DDQ = 2.5V 2.1 DDQ = 2.5V DDQ = 2.5V DDQ = 2.5V 1.7 V DDQ DD = 2.5V – ...
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... TH t TMSS t TMSH t TDIS t TDIH t TDOV CY7C1370CV25 CY7C1372CV25 010 010 01011001000010101 Reserved for future use. 00000110100 00000110100 1 1 CY7C1370CV25 CY7C1372CV25 (continued) Min. Max ALL INPUT PULSES 2.5V 1.25V 1 TCYC t TDOX Description Reserved for version number. Allows unique identification of SRAM vendor. ...
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... Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05235 Rev. *C Bit Size (x36 Description CY7C1370CV25 CY7C1372CV25 Page ...
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... BGA Boundary Scan Order CY7C1370CV25 (512K x 36) Bit# Ball ID Bit ...
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... Boundary Scan Order CY7C1370CV25 (512K x 36) Bit# Ball Id Bit B10 43 9 A10 44 10 C11 45 11 E10 46 12 F10 47 13 G10 48 14 D10 49 15 D11 50 16 E11 51 17 F11 ...
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... /2), undershoot: V (AC)> -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < CY7C1370CV25 CY7C1372CV25 Ambient Temperature V DD 0°C to +70°C 2.5V–5%/+5% 2.5V –5% to –40°C to +85°C Min. Max. 2.375 2.625 2.375 ...
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... SRAMs when sharing the same EOLZ CHZ CLZ CY7C1370CV25 CY7C1372CV25 BGA Max. fBGA Max. TQFP Max [16] ALL INPUT PULSES V DD 90% 1 ...
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... Min. Max. Min. Max. Min. Max. Min. Max. 1.2 1.2 1.2 1.2 0.3 0.3 0.3 0.3 0.3 0 CYC CLZ D(A1) D(A2) D(A2+1) BURST READ READ WRITE Q(A3) Q(A4) D(A2+1) DON’T CARE UNDEFINED is LOW. When CE is HIGH,CE is HIGH CY7C1370CV25 CY7C1372CV25 [ 21, 22] -225 -200 -167 1.4 1.4 1.5 1.4 1.4 1.5 1.4 1.4 1.5 1.4 1.4 1.5 0.4 0.4 0.5 0.4 0.4 0.5 0.4 0.4 0.5 0.4 0.4 0.5 0.4 0.4 0.5 0.4 0.4 0 ...
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... I/Os are in High-Z when exiting ZZ sleep mode. Document #: 38-05235 Rev. *C [23,24,26 D(A1) Q(A2) STALL READ WRITE STALL Q(A3) D(A4) DON’T CARE DDZZ High-Z DON’T CARE CY7C1370CV25 CY7C1372CV25 D(A4) Q(A3) NOP READ DESELECT Q(A5) UNDEFINED t ZZREC t RZZI DESELECT or READ Only 10 t CHZ Q(A5) CONTINUE ...
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... CY7C1370CV25-200AC CY7C1372CV25-200AC CY7C1370CV25-200BGC CY7C1372CV25-200BGC CY7C1370CV25-200BZC CY7C1372CV25-200BZC 167 CY7C1370CV25-167AC CY7C1372CV25-167AC CY7C1370CV25-167BGC CY7C1372CV25-167BGC CY7C1370CV25-167BZC CY7C1372CV25-167BZC Document #: 38-05235 Rev. *C Package Name Package Type A101 100-lead Thin Quad Flat Pack ( 1.4 mm) BG119 119-ball Ball Grid Array ( 2.4 mm) BB165A 165-ball Fine Pitch Ball Grid Array ( 1.2 mm) A101 100-lead Thin Quad Flat Pack ( ...
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... CY7C1372CV25-225BGI CY7C1370CV25-225BZI CY7C1372CV25-225BZI 200 CY7C1370CV25-200AI CY7C1372CV25-200AI CY7C1370CV25-200BGI CY7C1372CV25-200BGI CY7C1370CV25-200BZI CY7C1372CV25-200BZI 167 CY7C1370CV25-167AI CY7C1372CV25-167AI CY7C1370CV25-167BGI CY7C1372CV25-167BGI CY7C1370CV25-167BZI CY7C1372CV25-167BZI Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05235 Rev. *C Package Name Package Type A101 100-lead Thin Quad Flat Pack ( ...
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... MAX. 0.25 GAUGE PLANE R 0.08 MIN. 0°-7° 0.20 MAX. 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL Document #: 38-05235 Rev. *C DIMENSIONS ARE IN MILLIMETERS. 16.00±0.20 14.00±0. 0.30±0.08 0.65 TYP STAND-OFF 0.05 MIN. SEATING PLANE 0.15 MAX. A CY7C1370CV25 CY7C1372CV25 1.40±0.05 12°±1° A SEE DETAIL (8X) 0.20 MAX. 1.60 MAX. 51-85050-*A Page ...
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... Package Diagrams (continued) Document #: 38-05235 Rev. *C 119-Lead PBGA ( 2.4 mm) BG119 CY7C1370CV25 CY7C1372CV25 51-85115-*B Page ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1370CV25 CY7C1372CV25 51-85122-*C ...
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... Document History Page Document Title: CY7C1370CV25/CY7C1372CV25 512K x 36/ Pipelined SRAM with NoBL™ Architecture Document Number: 38-05235 REV. ECN No. Issue Date ** 116273 08/27/02 *A 121536 11/21/02 *B 206100 see ECN *C 231349 See ECN Document #: 38-05235 Rev. *C Orig. of Change Description of Change SKX New Data Sheet DSG Updated package diagrams 51-85115 (BG119) to rev ...