AD9802JST Analog Devices, AD9802JST Datasheet

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AD9802JST

Manufacturer Part Number
AD9802JST
Description
Manufacturer
Analog Devices
Datasheet

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PRODUCT DESCRIPTION
The AD9802 is a complete CCD signal processor developed
for electronic cameras. It is suitable for both camcorder and
consumer-level still camera applications.
The signal processing chain is comprised of a high speed CDS,
variable gain PGA and 10-bit ADC. Required clamping cir-
cuitry and an onboard voltage reference are provided as well as a
direct ADC input. The AD9802 operates from a single +3 V
supply with a typical power consumption of 185 mW.
The AD9802 is packaged in a space saving 48-terminal thin
quad flatpack (TQFP) and is specified over an operating tem-
perature range of 0 C to +70 C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
10-Bit, 18 MSPS A/D Converter
18 MSPS Full Speed Correlated Double Sampler (CDS)
Low Noise, Wideband PGA
Internal Voltage Reference
No Missing Codes Guaranteed
+3 V Single Supply Operation
Low Power CMOS: 185 mW
48-Terminal TQFP Package
PRODUCT HIGHLIGHTS
1. On-Chip Input Clamp and CDS
2. On-Chip PGA
3. Direct ADC Input
4. 10-Bit, High Speed A/D Converter
5. Low Power
6. Digital I/O Functionality
7. Small Package
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
ADCIN
PIN
DIN
Clamp circuitry and high speed correlated double sampler
allow for simple ac-coupling to interface a CCD sensor at full
18 MSPS conversion rate.
The AD9802 includes a low-noise, wideband amplifier with
analog variable gain from 0 dB to 31.5 dB (linear in dB).
A direct input to the 10-bit A/D converter is provided for
digitizing video signals.
A linear 10-bit ADC is capable of digitizing CCD signals at
the full 18 MSPS conversion rate. Typical DNL is 0.5 LSB
and no missing code performance is guaranteed.
At 185 mW, and 15 mW in power-down, the AD9802 con-
sumes a fraction of the power of presently available multichip
solutions.
The AD9802 offers three-state digital output control.
Packaged in a 48-terminal, surface-mount thin quad flatpack,
the AD9802 is well suited to very compact, low headroom
designs.
CMLEVEL VRT VRB STBY
PBLK
REFERENCE
FUNCTIONAL BLOCK DIAGRAM
CLPDM
CLAMP
CDS
For Electronic Cameras
CCD Signal Processor
World Wide Web Site: http://www.analog.com
PGACONT1 PGACONT2
PGA
CLPOB
CLAMP
MUX
ADCMODE
© Analog Devices, Inc., 1997
S/H
SHP
AD9802
ACVDD
GENERATOR
AD9802
TIMING
SHD ADCCLK
A/D
ADVDD
10
DRVDD
DVDD
DOUT

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AD9802JST Summary of contents

Page 1

... C to +70 C. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...

Page 2

AD9802–SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE (For Functional Operation) ACVDD ADVDD DVDD DRVDD POWER SUPPLY CURRENT ACVDD ADVDD DVDD DRVDD POWER CONSUMPTION Normal Operation Power-Down Mode MAXIMUM SHP, SHD, ADCCLK RATE ADC Resolution Differential Nonlinearity No Missing ...

Page 3

... Exposure to absolute maximum ratings for extended periods may affect device reliability. Model Temperature Range AD9802JST +70 C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...

Page 4

AD9802 CONNECT Pin # Pin Name Type 1 ADVSS P 2–11 D0– DRVDD P 13 DRVSS P 14 DSUBST P 15 DVSS P 16 ADCCLK DI 17 DVDD P 18 STBY DI 19 PBLK DI ...

Page 5

EQUIVALENT INPUT CIRCUITS DVDD DVSS Figure 1. Pins 2–11 (DB0–DB9) DVDD 200 DSUBST Figure 2. Pin 21 (SHP) and Pin 22 (SHD) DVDD 200 DSUBST Figure 3. Pin 16 (ADCCLK) ADVDD 9.3k ADVSS Figure 4. Pin 37 (CMLEVEL) ACVDD 50 ...

Page 6

AD9802 EFFECTIVE PIXEL INTERVAL CCD SHP SHD CLPOB PBLK CLPDM ADCCLK ADC DATA NOTES: CLPDM AND CLPOB OVERWRITE PBLK CLAMP TIMING NEEDS TO BE ADJUSTED RELATIVE TO CCD'S BLACK PIXELS RECOMMENDED PULSE WIDTH CLPDM = 1.5 s MIN BLACK DUMMY ...

Page 7

CCD SIGNAL (DELAYED TO MATCH ACTUAL SAMPLING EDGE) SHD SHP ACTUAL SAMPLING EDGE 35ns ADCCLK DIGITAL OUT OUTPUT LOAD C SHP SHD PRE-ADC OUTPUT LATCH PRE-ADC OUTPUT LATCH DATA TRANSITION ADCCLK REV N+2 N+1 ...

Page 8

AD9802 THEORY OF OPERATION Introduction The AD9802 is a 10-bit analog-to-digital interface for CCD cameras. The block level diagram of the system is shown in Figure 14. The device includes a correlated double sampler (CDS), 0 dB–31 dB variable gain ...

Page 9

The actual implementation of this loop is slightly more compli- cated as shown in Figure 19. Because there are two separate CDS blocks, two black level feedback loops are required and two offset voltages are developed. Figure 19 also shows ...

Page 10

AD9802 APPLICATIONS INFORMATION Generating Clock Signals For best performance, the AD9802 should be driven logic levels. As shown in the Equivalent Input Circuits, the use logic for ADCCLK will turn on the protection diode ...

Page 11

... Digitally Programmable Gain Control The AD9802’s PGA is controlled by an analog input voltage some applications, digital gain control is preferable. Figure 30 shows a circuit using Analog Devices’ AD8402 Digital Potentiometer to generate the PGA control voltage. The AD8402 functions as two individual potentiom- eters, with a serial digital interface to program the position of each wiper over 256 positions ...

Page 12

... AD820, OP150 and OP196 are speci- fied for 3 V operation. Alternatively, a precision voltage refer- ence may be used. The REF193 from Analog Devices features low power, low dropout performance, maintaining output with a minimum 3.1 V supply when lightly loaded. ...

Page 13

Jumper Descriptions JP1 Connect to bypass the input coupling capacitor C18. JP2 Connect to short PIN and DIN (Pins 26 and 27 of the AD9801) together. JP3 Connects PIN to the dc level set by the wiper of R1. JP4 ...

Page 14

AD9802 VDD C4 C55 0 0.1 F ADVSS (LSB ...

Page 15

TP12 +3V FB1 J1 C34 0.1 F TP13 +5V FB2 J2 C37 0.1 F TP14 –5V FB3 J3 C40 0.1 F TP15 GND J4 TP16 DGND J5 TP17 +3D FB4 J6 C43 0.1 F TP18 +3/5D FB5 J7 C46 0.1 ...

Page 16

AD9802 +3D +3/5D C26 C53 74LVXC3245 0 ...

Page 17

REV. 0 Figure 34. Primary Side (Layer 1) Figure 35. Ground Plane (Layer 2) –17– AD9802 ...

Page 18

AD9802 Figure 36. Power Plane (Layer 3) Figure 37. Secondary Layer (Layer 4) –18– REV. 0 ...

Page 19

REV. 0 Figure 38. Primary Side Assembly Figure 39. Secondary Side Assembly –19– AD9802 ...

Page 20

AD9802 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Terminal Plastic Thin Quad Flatpack (TQFP) (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC 0.030 (0.75) 0.057 (1.45) 0.276 (7.0) BSC 0.030 (0.75) 0.018 (0.45) 0.053 (1.35) 0.018 (0.45 SEATING ...

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