UPD784021GC-3B9 Renesas Electronics Corporation., UPD784021GC-3B9 Datasheet
UPD784021GC-3B9
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UPD784021GC-3B9 Summary of contents
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SINGLE-CHIP MICROCOMPUTER The m PD784021 is a product of the m PD784026 sub-series in the 78K/IV series. It contains various peripheral hardware such as RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interface, and interrupt functions, ...
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ORDERING INFORMATION Part number m PD784020GC-3B9 80-pin plastic QFP (14 ¥ 14 mm) m PD784021GC-3B9 80-pin plastic QFP (14 ¥ 14 mm) m PD784021GK-BE9 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM : Product ...
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FUNCTIONS Product Item Number of basic instructions 113 (mnemonics) 8 bits ¥ 16 registers ¥ 8 banks bits ¥ 8 registers ¥ 8 banks (memory mapping) General-purpose register 160 ns/320 ns/640 ns/1280 ns (at 25 MHz) Minimum instruction ...
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DIFFERENCES BETWEEN PD784026 SUB-SERIES ........................................................... 1. MAIN DIFFERENCES BETWEEN PD784026 AND PD78234 SUB-SERIES ..................... 2. 3. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 4. SYSTEM CONFIGURATION EXAMPLE ...
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LOCAL BUS INTERFACE ......................................................................................................... 10.1 MEMORY EXPANSION .................................................................................................................. 10.2 MEMORY SPACE ........................................................................................................................... 10.3 PROGRAMMABLE WAIT ............................................................................................................... 10.4 PSEUDO-STATIC RAM REFRESH FUNCTION ........................................................................... 10.5 BUS HOLD FUNCTION .................................................................................................................. 11. STANDBY FUNCTION .............................................................................................................. 12. RESET FUNCTION .................................................................................................................... 13. INSTRUCTION SET ................................................................................................................... ...
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DIFFERENCES BETWEEN PD784026 SUB-SERIES The only difference between the m PD784020, m PD784021, m PD784025, and m PD784026 is their capacity of internal memory, port functions, and part of their packages. The m PD78P4026 ...
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MAIN DIFFERENCES BETWEEN PD784026 AND PD78234 SUB-SERIES Series Item Number of basic instructions 113 (mnemonics) Minimum instruction execution 160 ns time (at 25 MHz) Memory space (program/data) 1M byte ...
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PIN CONFIGURATION (TOP VIEW) • 80-pin plastic QFP (14 ¥ 14 mm) m PD784020GC-3B9, m PD784021GC-3B9 • 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) m PD784021GK-BE9 ...
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P00-P07 : Port 0 P10-P17 : Port 1 P20-P27 : Port 2 P30-P37 : Port 3 P60-P63, P66, P67 : Port 6 P70-P77 : Port 7 TO0-TO3 : Timer output CI : Clock input RxD, RxD2 : Receive data TxD, ...
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SYSTEM CONFIGURATION EXAMPLE (PPC) Serial communication PD27C1001A OE CE A8-A16 O0-O7 PD74HC573 A0-A7 Sensing paper transport Temperature of the fusing heater Brightness of the lamp Lever for adjusting the tone of the copy Lever for compensating the tone of ...
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BLOCK DIAGRAM NMI Programmable interrupt controller INTP0-INTP5 INTP3 Timer/counter 0 TO0 (16 bits) TO1 Timer/counter 1 INTP0 (16 bits) INTP1 INTP2/CI Timer/counter 2 TO2 (16 bits) TO3 Timer 3 (16 bits) P00-P03 Real-time output port P04-P07 PWM0 PWM PWM1 ...
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LIST OF PIN FUNCTIONS 6.1 PORT PINS Pin I/O Dual-function P00-P07 I/O — P10 I/O PWM0 P11 PWM1 P12 ASCK2/SCK2 P13 RxD2/SI2 P14 TxD2/SO2 P15-P17 — P20 Input NMI P21 INTP0 P22 INTP1 P23 INTP2/CI P24 INTP3 P25 INTP4/ASCK/SCK1 ...
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NON-PORT PINS (1/2) Pin I/O Dual-function TO0-TO3 Output P34-P37 CI Input P23/INTP2 R D Input P30/SI1 P13/SI2 Output P31/SO1 P14/SO2 X ASCK Input P25/INTP4/SCK1 ASCK2 P12/SCK2 SB0 I/O P33/SO0 SI0 ...
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NON-PORT PINS (2/2) Pin I/O Dual-function RESET Input — X1 Input — X2 — ANI0-ANI7 Input P70-P77 ANO0, ANO1 Output — AV — — REF1 REF2 REF3 TEST ...
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I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS Table 6-1 describes the types of I/O circuits for pins and the handling of unused pins. Fig. 6-1 shows the configuration of these various types of I/O circuits. Table 6-1 ...
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Table 6-1 Types of I/O Circuits for Pins and Handling of Unused Pins (2/2) Pin I/O circuit type RESET 2 TEST 1 AV -AV — REF1 REF3 Caution When the I/O mode of an I/O dual-function ...
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Type Type 2 IN Schmitt trigger input with hysteresis characteristics V Type 4 DD Data P Output N disable Push-pull output which can output high impedance (both the positive and negative channels are off.) ...
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CPU ARCHITECTURE 7.1 MEMORY SPACE A 1M-byte memory space can be accessed. By using a LOCATION instruction, the mode for mapping internal data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be ...
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PD784020, 784021 1 9 ...
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PD784020, 784021 ...
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CPU REGISTERS 7.2.1 General-Purpose Registers A set of general-purpose registers consists of sixteen general-purpose 8-bit registers. Two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with an 8-bit ...
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Control Registers (1) Program counter (PC) This register is a 20-bit program counter. The program counter is automatically updated by program execution. Fig. 7-4 Format of Program Counter (PC (2) Program Status Word (PSW) This register holds ...
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Special Function Registers (SFRs) The special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H and 0FFFFH Note ...
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Table 7-1 Special Function Registers (SFRs) (1/4) Address Note Special function register (SFR) name 0FF00H Port 0 0FF01H Port 1 0FF02H Port 2 0FF03H Port 3 0FF06H Port 6 0FF07H Port 7 0FF0EH Port 0 buffer register L P0L 0FF0FH ...
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Table 7-1 Special Function Registers (SFRs) (2/4) Address Note Special function register (SFR) name 0FF36H Capture register (timer/counter 0) 0FF38H Capture register L (timer/counter 1) 0FF39H Capture register H (timer/counter 1) 0FF3AH Capture register L (timer/counter 2) 0FF3BH Capture register ...
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Table 7-1 Special Function Registers (SFRs) (3/4) Address Note 1 Special function register (SFR) name 0FF84H Synchronous serial interface mode register 1 0FF85H Synchronous serial interface mode register 2 0FF86H Serial shift register 0FF88H Asynchronous serial interface mode register 0FF89H ...
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Table 7-1 Special Function Registers (SFRs) (4/4) Address Note Special function register (SFR) name 0FFCCH Refresh mode register 0FFCDH Refresh area specification register 0FFCFH Oscillation settling time specification register 0FFD0H- External SFR area 0FFDFH 0FFE0H Interrupt control register (INTP0) 0FFE1H ...
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PERIPHERAL HARDWARE FUNCTIONS 8.1 PORTS The ports shown in Fig. 8-1 are provided to enable the application of wide-ranging control. Table 8-1 lists the functions of the ports. For the inputs to port 0 to port 6, a built-in ...
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Port name Pin Port 0 P00-P07 • Bit-by-bit input/output setting supported • Operable as 4-bit real-time outputs (P00-P03, P04-P07) • Capable of driving transistors Port 1 P10-P17 • Bit-by-bit input/output setting supported • Capable of driving LEDs Port 2 P20-P27 ...
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Fig. 8-3 Examples of Using Oscillator • When EXTC bit of OSTS = 1 PD784021 X1 X2 PD74HC04, etc. Caution When using the clock generator, to avoid problems caused by influences such as stray capacitance, run all wiring within the ...
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REAL-TIME OUTPUT PORT The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. Thus, pulse output that is free of jitter can be obtained. Therefore, the real-time output port ...
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TIMERS/COUNTERS Three timer/counter units and one timer unit are incorporated. Moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units. Table 8-2 Timer/Counter Operation Item Count pulse width 8 bits 16 bits Operating mode ...
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Fig. 8-5 Timer/Counter Block Diagram Timer/counter Prescaler xx Edge INTP3 detection INTP3 Timer/counter Prescaler xx Event input Edge INTP0 detection INTP0 Timer/counter Prescaler xx INTP2/C1 Edge detection INTP2 Edge INTP1 detection ...
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PWM OUTPUT (PWM0, PWM1) Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 48.8 kHz (f = 12.5 MHz) are incorporated. Low or high active level can be ...
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A/D CONVERTER An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0-ANI7) is incorporated. The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D conversion result register (ADCR). Thus, speedy high-precision ...
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D/A CONVERTER Two digital/analog (D/A) converter channels of voltage output type, having a resolution of 8 bits, are incorporated. A resistor string system is used for conversion. By writing the value to be subject to D/A conversion in the ...
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SERIAL INTERFACE Three independent serial interface channels are incorporated. • Asynchronous serial interface (UART)/three-wire serial I/O (IOE) ¥ 2 • Synchronous serial interface (CSI) ¥ 1 • Three-wire serial I/O (IOE) • Serial bus interface (SBI) So, communication with ...
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Asynchronous Serial Interface/Three-Wire Serial I/O (UART/IOE) Two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire serial I/O mode can be selected. (1) Asynchronous serial interface mode In this mode, 1-byte data is transferred ...
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Three-wire serial I/O mode In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. This mode is designed for communication with a device incorporating a conventional ...
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Synchronous Serial Interface (CSI) With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. Fig. 8-12 Block Diagram of Synchronous Serial Interface SI0 SO0/SB0 N-ch open-drain ...
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Three-wire serial I/O mode This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK0) and serial data lines (SI0 and SO0). In ...
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WATCHDOG TIMER A watchdog timer is incorporated for CPU runaway detection. The watchdog timer, if not cleared by software within a specified interval, generates a nonmaskable interrupt. Furthermore, once watchdog timer operation is enabled, it cannot be disabled by ...
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INTERRUPT FUNCTION Table 9-1 lists the interrupt request handling modes. These modes are selected by software. Table 9-1 Interrupt Request Handling Modes Handling mode Handled by Vectored interrupt Software Branches to a handling routine for execution (arbitrary handling). Context ...
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Default Type priority Name Software – BRK instruction Operand error Nonmaskable – NMI WDT Maskable 0 (highest) INTP0 1 INTP1 2 INTP2 3 INTP3 4 INTC00 5 INTC01 6 INTC10 7 INTC11 8 INTC20 9 INTC21 10 INTC30 11 INTP4 ...
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VECTORED INTERRUPT When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt source is used as the branch address. Interrupt handling by the CPU consists of the following operations : • When ...
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CONTEXT SWITCHING When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the ...
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EXAMPLES OF MACRO SERVICE APPLICATIONS (1) Serial interface transmission TxD Each time a macro service request (INTST) is generated, the next transmission data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS ...
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Real-time output port INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used to ...
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LOCAL BUS INTERFACE The local bus interface enables the connection of external memory and I/O devices (memory-mapped I/O). It supports a 1M-byte memory space. (See Fig. 10-1.) Fig. 10-1 Example of Local Bus Interface PD784021 A16-A19 RD WR REFRQ ...
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MEMORY SPACE The 1M-byte memory space is divided into eight spaces, each having a logical address. Each of these spaces can be controlled using the programmable wait and pseudo-static RAM refresh functions. FFFFFH 80000H 7FFFFH 40000H 3FFFFH 20000H 1FFFFH ...
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PROGRAMMABLE WAIT When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the signal is active. This prevents the overall system efficiency from being degraded ...
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STANDBY FUNCTION The standby function allows the power consumption of the chip to be reduced. The following standby modes are supported: • HALT mode : The CPU operation clock is stopped. By occassionally inserting the HALT mode during normal ...
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RESET FUNCTION Applying a low-level signal to the RESET pin initializes the internal hardware (reset status). When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC): • Eight low-order bits of ...
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INSTRUCTION SET (1) 8-bit instructions (The instructions enclosed in parentheses are implemented by a combination of operands, where A is described as r.) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, ...
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AX is described as rp.) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, ...
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WHL is described as rg.) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 13-3 Instructions Implemented by 24-Bit Addressing 2nd operand #imm24 WHL 1st ...
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Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET Table 13-4 Bit Manipulation Instructions Implemented by Addressing 2nd operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit 1st operand !addr16.bit !!addr24.bit CY MOV1 AND1 ...
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Call/return instructions and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, ...
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ELECTRICAL CHARACTERISTICS The electrical characteristics described in this chapter apply to the products which are improved versions of the m PD784020 and m PD784021 (other than K-rank products). For K-rank products yet to be improved (K-rank products), please consult ...
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OPERATING CONDITIONS • Operating ambient temperature (T ): –40 to +85 °C A • Rising and falling time ( (for pins not especially specified 200 • Power supply voltage and clock ...
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OSCILLATOR CHARACTERISTICS (T Resonator Recommended circuit Ceramic resonator or crystal External clock X1 HCMOS Inverter Caution When using the system clock generator, run wires in the portion surrounded by dotted lines according to the following rules ...
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OSCILLATOR CHARACTERISTICS (T Resonator Recommended circuit Ceramic resonator or crystal External clock X1 HCMOS Inverter Caution When using the system clock generator, run wires in the portion surrounded by dotted lines according to the following rules ...
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DC CHARACTERISTICS (T = –40 to +85 ° Parameter Symbol Low-level input voltage V Pins other than those described in IL1 Notes and 4 V Pins described in Notes and 4 IL2 ...
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DC CHARACTERISTICS (T = –40 to +85 ° Parameter Symbol 0 V £ V Input leakage current I LI Except for the X1 pin when EXTC = £ V Analog input pins 0 V £ ...
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AC CHARACTERISTICS (T = –40 to +85 ° (1) Read/write operation (1/2) Parameter Symbol Address setup time t V SAST DD ASTB high-level width t V WSTH DD Address hold time t V HSTLA DD (referred to ASTBØ) ...
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Read/write operation (2/2) Parameter Symbol Data setup time t V SODW (referred to WR•) Data hold time t V HWOD Note (referred to WR•) WR• Æ ASTB• delay time t DWST WR low-level width t V WWL Note The ...
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External wait timing Parameter Symbol Address Æ WAITØ input time t V DAWT DD ASTBØ Æ WAITØ input time t V DSTWT DD ASTBØ Æ WAIT hold time t V HSTWTH DD ASTBØ Æ WAIT• delay time t V ...
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SERIAL OPERATION (CSI) Parameter Symbol Serial clock cycle time t Input CYSK0 (SCK0) Output Serial clock low-level width t Input WSKL0 (SCK0) Output Serial clock high-level width t Input WSKH0 (SCK0) Output SI0, SB0 setup time t SSSK0 (referred to ...
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SERIAL OPERATION (IOE1, IOE2) Symbol Parameter Serial clock cycle time t Input CYSK1 (SCK1, SCK2) Output t Serial clock low-level width Input WSKL1 (SCK1, SCK2) Output t Serial clock high-level width Input WSKH1 (SCK1, SCK2) Output SI1, SI2 setup time ...
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OTHER OPERATIONS Parameter Symbol NMI low-level width t WNIL NMI high-level width t WNIH INTP0 low-level width t WIT0L INTP0 high-level width t WIT0H INTP1-INTP3 and CI low- t WIT1L level width INTP1-INTP3 and CI high- t WIT1H level width ...
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D/A CONVERTER CHARACTERISTICS (T Parameter Symbol Resolution Note Total error Load condition Load condition Settling time Load condition Output resistance R O Analog reference voltage AV REF2 AV ...
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DATA RETENTION CHARACTERISTICS (T Parameter Symbol Data retention voltage V STOP mode DDDR Data retention current I V DDDR V V rising time t DD RVD V falling time t DD FVD V retention time t DD HVD (referred to ...
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Timing Waveform (1) Read operation t WSTH ASTB t SAST t HSTLA A8-A19 AD0-AD7 t DSTR t DAR RD (2) Write operation t WSTH ASTB t SAST t HSTLA A8-A19 AD0-AD7 t DSTW t DAW WR t DSTID t DAID ...
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Hold Timing ASTB, A8-A19, AD0-AD7, RD FHQC t DCFHA HLDRQ t DHQHHAH HLDAK External WAIT Signal Input Timing (1) Read operation ASTB t DSTWT A8-A19 AD0-AD7 t DAWT RD WAIT (2) Write operation ASTB t DSTWT A8-A19 AD0-AD7 ...
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Timing Waveform for Refresh (1) Random read/write cycle t RC ASTB (2) When a refresh is performed simultaneously with a memory access ASTB RD DSTRFQ REFRQ (3) Refresh after reading ASTB RD REFRQ (4) ...
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Serial Operation (CSI) (1) Three-wire serial I/O mode t WSKL0 SCK t CYSK0 SI SO (2) SBI mode Ý Bus release signal transfer SCK t t HSBSK2 WSBL SB0 Ý Command signal transfer SCK t t HSBSK2 SSBSK SB0 7 ...
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Serial Operation (IOE1, IOE2) t WSKL1 SCK t CYSK1 SI SO Serial Operation (UART, UART2) ASCK, ASCK2 PD784020, 784021 t WSKH1 t SSSK1 Input data t t DSOSK HSOSK Output data t t WASKH WASKL ...
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Interrupt Input Timing NMI INTP0 CI, INTP1-INTP3 INTP4, INTP5 Reset Input Timing RESET WNIH WNIL 0. WIT0H WIT0L 0. WIT1H WIT1L 0. ...
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External Clock Timing 0. 0 Data Retention Timing Set STOP mode HVD FVD RESET NMI (Released by a falling edge) NMI (Released by a rising edge) t WXH ...
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PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14 14 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. Remark The shape and ...
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PIN PLASTIC TQFP (FINE PITCH NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. Remark The shape and material of the ...
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RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the m PD784021. For details of the recommended soldering conditions, refer to our document SMD Surface Mount Technology Manual (C10535E) . Please consult with our sales offices ...
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APPENDIX A DEVELOPMENT TOOLS The following development tools are available for system development using the m PD784021. Language Processing Software Note 1 RA78K4 Note 1 CC78K4 Note 1 CC78K4-L PROM Write Tools PG-1500 PA-78P4026GC PA-78P4038GK PA-78P4026KK Note 2 PG-1500 controller ...
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Notes 1. Based on PC-9800 series (MS-DOS • Based on IBM PC/AT and compatibles (PC DOS • Based on HP9000 series 700 • Based on SPARCstation • TM Based on NEWS (NEWS-OS • 2. Based on PC-9800 series (MS-DOS) ...
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APPENDIX B RELATED DOCUMENTS Documents Related to Devices Document name m PD784020, 784021 Data Sheet m PD784025, 784026 Data Sheet m PD78P4026 Data Sheet m PD784026 Sub-Series User's Manual, Hardware m PD784026 Sub-Series Special Function Registers m PD784026 Sub-Series Application ...
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Documents Related to Software to Be Incorporated into the Product (User’s Manual) Document name 78K/IV Series Real-Time OS OS for 78K/IV Series MX78K4 Other Documents Document name IC PACKAGE MANUAL SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor ...
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PD784020, 784021 8 7 ...
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Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged. Strong static electricity may cause dielectric breakdown in gates. When transporting or storing MOS devices, use conductive trays, magazine ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated in this document. No part of this document may be copied or reproduced in any form or by any means without the prior ...