S5L9286F01-Q0R0 Samsung, S5L9286F01-Q0R0 Datasheet
S5L9286F01-Q0R0
Related parts for S5L9286F01-Q0R0
S5L9286F01-Q0R0 Summary of contents
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... Digital audio output • Digital de-emphasis • ESP interface • Built-in 16K SRAM • Built-in digital PLL • Double speed play available • Built-in 16-bit D/A converter • ORDERING INFORMATION Device S5L9286F01-Q0R0 Package 80-QFP-1420C S5L986F01 80-QFP-1420C Tempe. Range o o -20 C – + ...
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... S5L9286F01 BLOCK DIAGRAM EFMI 66 PHASE DETECTOR CNTVOL 5 DIGITAL PLL DPFIN 3 DPFOUT 4 DPDO 2 SMEF 72 SMON 73 CLV SERVO SMDP 75 SMDS 76 LOCK 70 XOUT 9 XIN 8 MDAT 37 MCK 38 INTERFACE MLT 36 TRCNT 69 /ISTAT 68 SELECTOR SUBCODE SUBCODE SYNC OUTPUT DETECTOR EFM 23BIT SHIFT DEMODULATOR REGISTER ...
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... AVDD2 18 RCHOUT 19 LCHOUT 20 AVSS2 21 VREFH1 22 VREFH2 23 EMPH S5L9286F01 S5L986F01 SRAM CDROM FOK XTALSEL /CS /WE C16M C4M /JIT ULKFS FSDW DVSS2 /PBCK ...
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... S5L9286F01 PIN DESCRIPTION PIN NO SYMBOL IO 1 AVDD1 - 2 DPDO O 3 DPFIN I 4 DPFOUT O 5 CNTVOL I 6 AVSS1 - 7 DATX O 8 XIN I 9 XOUT O 10 WDCHO O 11 LRCHO O 12 ADATAO O 13 DVSS1 - 14 BCKO O 15 C2PO O 16 VREFL2 I 17 VREFL1 I 18 AVDD2 - 19 RCHOUT O 20 LCHOUT ...
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DIGITAL SIGNAL PROCESSOR FOR CDP PIN DESCRIPTION (continued) PIN NO SYMBOL IO 30 SQDT O 31 SQOK O 32 SBCK I 33 SDAT O 34 DVDD1 - 35 MUTE I 36 MLT I 37 MDAT I 38 MCK I 39 ...
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... S5L9286F01 PIN DESCRIPTION (continued) PIN NO SYMBOL IO 61 XTALSEL I 62 FOK I 63 CDROM I 64 SRAM I 65 TEST1 I 66 EFMI I 67 ADATAI I 68 /ISTAT O 69 TRCNT I 70 LOCK O 71 PBFR O 72 SMEF O 73 SMON O 74 DVDD2 - 75 SMDP O 76 SMDS O 77 BCKI I 78 TESTV ...
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DIGITAL SIGNAL PROCESSOR FOR CDP ABSOLUTE MAXIMUM RATINGS Characteristic Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature ELECTRICAL CHARACTERISTIC DC Characteristic o (Vcc = 5V, Vss = 0V, Ta=25 , unless otherwise specified) C Item Symbol High input ...
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... S5L9286F01 AC Characteristic When pulse is input to XIN, VCOI pin (Vcc=5V, Vss=0V, Ta=25 Item High Level Pulse Width High Level Pulse Width Pulse Frequency Input High Level Input Low Level Rising & Falling Time TR 8 DIGITAL SIGNAL PROCESSOR FOR CDP o , unless otherwise specified) C Symbol ...
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DIGITAL SIGNAL PROCESSOR FOR CDP MCK, MDAT, MLT & TRCNT (Vcc=5V, Vss=0V, Ta=25 Characteristic Clock Frequency Clock Pule Width Setup Time Hold Time Delay Time Latch Pulse Width TRCNT, SQCK Frequency TRCNT, SQCK Pulse Width MCK MDAT MLT TRCNT SQCK ...
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... S5L9286F01 FUNCTION DESCRIPTION Micom Interface The data inputted from Micom is inputted to MDAT and transfered by MCK, and the inputted signal is loaded to control register by means of MLT. The timing chart is as follows. MDAT D0 D1 MCK MLT Register (9X ~ FX) MDAT D0 D1 MCK MLT Register (88XX, 8DXX) ...
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DIGITAL SIGNAL PROCESSOR FOR CDP CONTROL REGISTER DESCRIPTION • CNTL-Z This register carries out the following functions: audios zero cross mute, phase pin control, phase servos control signal management, and the decision whether or not to include SQOK data in ...
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... S5L9286F01 • CNTL-S This register sets the frame sync protection and attenuation. FWSEL of CNTL-D is added to define window size. . Bit 3 Identifier FSEM FSEM, FSEL Frame sync protection WSEL Frame Sync protection window size 0 ± ± 7T ...
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DIGITAL SIGNAL PROCESSOR FOR CDP • CNTL-W This register sets the CLV-Servos control period and gain.. Bit 3 Identifier - WB Bottom hold period control in speed mode 0 XTFT/32 1 XTFR/16 WP Peak hold period control in speed mode ...
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... S5L9286F01 • CNTL-D This register sets the normal speed and double speed mode. Bit 3 Identifier . Speed control • CNTL-E This register controls the de-emphasis. Bit 3 Identifier . CLV-servo mode control. Refer CNTL-W Register NOTE: D1 bit becomes to “L” when reset. MICOM must give the commands of attenuation and mute, when forward / backward searching ...
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DIGITAL SIGNAL PROCESSOR FOR CDP TRACKING COUNTER BLOCK When the number of tracks to be jumped is input from MICOM, the track number is loaded from MLTs positive edge to the register. If CNTL-L is selected, /COMPLETE signal is output ...
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... S5L9286F01 EFM DEMODULATION The EFM block is composed of the following parts: EFM demodulator to demodulate the EFM signal read from the disc, EFM phase detector, and the control signal generator. EFM DEMODULATOR The modulated 14 channel bit data is demodulated into 8-bit data. There are two types of demodulated data: subcode data and audio data ...
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DIGITAL SIGNAL PROCESSOR FOR CDP FRAME SYNC DETECT/PROTECT/INSERT • Frame Sync Detect Data is composed of units of frame, and a frame is composed of frame sync, subcode data, audio data, and redundancy data. This IC detects frame sync to ...
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... S5L9286F01 SUBCODE BLOCK The subcode sync signals S0 and S1 are detected in the Subcode sync block detected one frame after S0 is detected. At this time, S0+S1 signal is output to the S0S1 pin, and when the S0S1 signal is high, the S0S1 signal is output to the SDAT pin. Out of the data input into the EFMI pin, the 14-bit subcode data is EFM demodulated to 8- bit ( subcode data, synchronized with the WBCK signal, and output to SDAT by the SBCK clock ...
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DIGITAL SIGNAL PROCESSOR FOR CDP ERROR CORRECTING CODE (ECC) When disc data is damaged corrected using the ECC (Error Correcting Code) block. It uses the CIRC (Cross Interleaved Reed-Solomon Code), correcting errors when C1 (32, ...
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... S5L9286F01 INTERPOLATOR / MUTE Interpolator If a burst error occurs on the disc, sometimes data cannot be corrected even if you carry out the ECC process. The Interpolator block uses the ECCs C2 pointer to interpolate the data. The audio data is input into the Data bus in the following order: for each L/R-ch: 8-bit C2 point, lower data 8 bits, and upper data 8 bits ...
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DIGITAL SIGNAL PROCESSOR FOR CDP Mute/Attenuation The audio data can be muted or weakened by the ATTM signal of the MUTE pin and CNTL-S register. • Zero Cross Mute The audio data is muted when the CNTL-Z registers ZCMT is ...
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... S5L9286F01 CLV SERVO CNTL-C, E, G1, G2, and G3 registers are selected to control the CLV (Constant Linear Velocity) servo using the data input from MICOM. Also, the design is such that the servo control is stable when setting the speed. When setting the speed, the /(Pw 64) signal can be detected from the /ISTAT pin only if the CNTL-D register is first set before the CNTL-C register is selected ...
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DIGITAL SIGNAL PROCESSOR FOR CDP Phase-Mode The phase mode is the mode to control the EFM phase. Phase difference between PBFR/4 and XTFR/4 is detected when NCLV of CNTL-Z register is "L",and phase difference between Read Base Counter/4 and Write ...
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... S5L9286F01 22T ph_pulse bh_pulse EFM Width J215(>22T) J214(>23T) PH F/F (>22T) PH F/F (>23T) BH F/F (>22T) BH F/F (>23T) Latch (22T) Latch (23T) SMDP Figure 8. SMDP Output When The Gain is High in Speed-mode 24 DIGITAL SIGNAL PROCESSOR FOR CDP 21T > Hi 22T) > 23T ...
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DIGITAL SIGNAL PROCESSOR FOR CDP DIGITAL FILTER The S5L9284E has a built-in FIR ( Finite Impulse Response) digital filter. This digital filter consists of 8fs over sampling filter. (A) Normal Speed Play Mode FIR (B) Doubll ...
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... S5L9286F01 FILTER CHARACTERISTIC Ripple in passband : within + 0.5dB Attenuation in stopband: below -42dB 26 DIGITAL SIGNAL PROCESSOR FOR CDP (a) NORMAL SPEED frequency (Fs) (b) DOUBLE SPEED frequency (Fs) Figure 10. Filter Characteristic Curve ...
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DIGITAL SIGNAL PROCESSOR FOR CDP DIGITAL AUDIO OUT This block serially outputs 2-channel and 16-bit data with the digital audio interface format as reference. Digital audio interface format for CD 191 0L: L-ch format including ...
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... S5L9286F01 Control Signal (1) Validity bit: shows the presence of error in 16-bit audio data: “H”=error, “L”=valid data (2) User definable bit: subcode data out SOS1 PBFR SBCK SBDT Figure 13. Digital Audio Data Out Timing Diagram (3) Channel status bit: subcode-Qs upper 4-bit data output, shows number of channels, pre-emphasis, copy, CDP- category, etc ...
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DIGITAL SIGNAL PROCESSOR FOR CDP DIGITAL PLL This device contains Digital PLL in order to obtain the stable channel clock for demodulating EFM signal. The block diagram of Digital PLL is as follows. Frequency Synthesizer X'tal EFMI Phase Low Pass ...
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... S5L9286F01 D/A CONVERTER (DIGITAL TO ANALOG CONVERTER) The S5L9284E has a built-in 16-bit D/A converter. Digital audio data is a 2's complement serial format (MSB sirst), Vref Terminal Vref, the reference voltage across a resister-ladder, is usually recommended with VrefH1=5V, VrefL1=0V. One way of avoiding an amplitude mismatching between the Vref and OP AMP input connected to the output converter is to reduce the analog output amplitude with VrefH2=5V and VrefL2=0V (At this time about 100 F capacitor should be connected from VreH1 and VrefL1 to GND) ...
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DIGITAL SIGNAL PROCESSOR FOR CDP DIGITAL DE-EMPHASIS The Emphasis/De-Emphasis circuit is used for improving S/N ration by decreasing high frequency noise in case of the frequency characteristic of signal not being changed. The digital de-emphasis circuit, which can de-emphasise the ...
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... S5L9286F01 ESP INTERFACE BLOCK INTRODUCTION Because the location of normal table CD Player used in family is fixed possible to play music stabilitable when the degree of damage on disc is in limit range. But in now general that user can hear music when moving by Walkman-CD Player. In this case, if user has been shocked suddenly, it often happens that music playing is unstable ...
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DIGITAL SIGNAL PROCESSOR FOR CDP That is, after EFM Demodulation, Error Correction and Interpolation block operation in double speed, audio data is inputted to ESP IC which is the anti-shock memory controller. Audio data received by ESP IC is saved ...
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... S5L9286F01 APPLICATION INFORMATION MICOM REGISTER The S5L9826F01 uses the exactly same MICOM command as S5L9282E (DSP+DAC) except one address addition. ADRESS: $88 DATA: D1(DEEM) H: When Internal Digital De-emphasis circuit is used. L: When External Analog De-emphasis circuit is used. D1 bit is cleared 'L' by Reset. During fast search, for example forward or backward, MICOM must order attenuation to DSP IC. ...
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DIGITAL SIGNAL PROCESSOR FOR CDP PACKAGE DIMENSION #80 0.80 23.90 + 0.30 20.00 + 0.20 80-QFP-1420C #1 0.35 + 0.10 0.15 MAX 0.80 S5L986F01 0-8 + 0.10 0.15 - 0.05 0.10 MAX 0.05 MIN (0.80) 2.65 + 0.10 3.00 MAX ...