W83877TF Winbond, W83877TF Datasheet
W83877TF
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W83877TF Summary of contents
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... W83877TF WINBOND I/O ...
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... TM demand of Windows 95 , which makes system resource allocation more efficient than ever. Another benefit of W83877TF is that it is pin-to-pin compatible to W83877F, and all of the 100-pin Winbond I/O IC family. Thus makes the design of applications very convenient and flexible. WINBOND I/O This function is especially valuable for notebook TM PC97 Hardware Design Guide ...
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... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit W83877TF Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt Enable ...
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... Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) Publication Release Date: March 1998 - 42 - W83877TF Version 0.61 ...
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... Aside from the above connections, the UART operates normally. This method allows the CPU to test the UART in a convenient way Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable CTS, Loopback RI input ( bit 2 of HCR) DCD . - 43 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read by the CPU CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... RX FIFO. TBR empty 1. TCTS = 1 2. TDSR = 1 3. FERI = 1 4. TDCD = 1 Publication Release Date: March 1998 - 46 - W83877TF Clear Interrupt - Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1. Write data into TBR 2 ...
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... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI) Publication Release Date: March 1998 - 47 - W83877TF 16 -1. The output frequency of Version 0.61 ...
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... Decimal divisor used to Percent error difference between generate 16X clock 2304 1536 1047 857 768 384 192 Note 1 4 Note 1 2 Note 1 1 Note 2 1 Publication Release Date: March 1998 - 48 - W83877TF desired and actual ** ** 0.18% 0.099 0.53 Version 0.61 ...
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... Loop-back controls for communications link fault isolation Break, parity, overrun, framing error simulation Programmable baud generator allows division of 1.8461 MHz and 24 MHz Maximum baud rate 921k bps for 14.768MHz and 1.5M bps for 24MHz Publication Release Date: March 1998 - 2 - W83877TF 16 -1) Version 0.61 ...
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... Immediate or automatic power-down mode for the power management All hardware power-on settings have internal pull-up or pull-down resistors as default value Dedicated Infrared Communication Pins Package: 100-pin QFP (W83877TF), and also 100-pin LQFP (W83877TD) Compatible with IEEE 1284 specification Compatible with IEEE 1284 specification Publication Release Date: March 1998 ...
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... W83877TF RIB 50 X DCDB 49 X DSRB 48 X CTSB DTRB ...
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... Master Reset. Active high low during normal operations. Active low chip select signal. System address bus enable. CPU I/O read signal. CPU I/O write signal. DMA request signal B. DMA Acknowledge signal B. Publication Release Date: March 1998 - 5 - W83877TF Version 0.61 ...
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... For the legacy power management, the SMI is active low 200ns for the power management events, which generate an SMI interrupt in the legacy power management mode. This SMI output is enabled by setting the SMI_EN bit in CR3A register. DMA acknowledge signal A. DMA request signal A. Publication Release Date: March 1998 - 6 - W83877TF Version 0.61 ...
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... FDC. While Low, FDC PnP-related register (CR20) is set i.e. FDC is disabled. While High, CR20 is set to the default value, i.e. FDC is enabled recommended when intends to pull down at power-on reset. Publication Release Date: March 1998 - 7 - W83877TF is recommended Version 0.61 ...
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... This pin is for Extension FDD B; the function of this pin is the same as that of the MOB pin. EXTENSION 2FDD MODE: MOB2 This pin is for Extension FDD A and B; the function of this pin is the same as that of the MOB pin. Publication Release Date: March 1998 - 8 - W83877TF is recommended Version 0.61 ...
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... EXTENSION FDD MODE: WE2 This pin is for Extension FDD B; its functions are the same as those of the WE pin. EXTENSION 2FDD MODE: WE2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the WE pin. Publication Release Date: March 1998 - 9 - W83877TF Version 0.61 ...
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... EXTENSION FDD MODE: DIR2 This pin is for Extension FDD B; its function is the same as that of the DIR pin. EXTENSION 2FDD MODE: DIR2 This pin is for Extension FDD A and B; its function is the same as that of the DIR pin. Publication Release Date: March 1998 - 10 - W83877TF Version 0.61 ...
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... This pin is for Extension FDD B; the function of this pin is the same as that of the INDEX pin. This pin is pulled high internally. EXTENSION 2FDD MODE: INDEX2 This pin is for Extension FDD A and B; this function of this pin is the same as INDEX pin. This pin is pulled high internally. Publication Release Date: March 1998 - 11 - W83877TF Version 0.61 ...
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... RDATA pin. This pin is pulled high internally. EXTENSION 2FDD MODE: RDATA2 This pin is for Extension FDD A and B; this function of this pin is the same as that of the RDATA pin. This pin is pulled high internally. Publication Release Date: March 1998 - 12 - W83877TF Version 0.61 ...
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... Parallel port data bus bit 7. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: NC pin EXTENSION 2FDD MODE: DSA2 This pin is for Extension FDD A; its function is the same as that of the DSA pin. Publication Release Date: March 1998 - 13 - W83877TF Version 0.61 ...
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... CR6 (FIPURDWN). Diskette change. This signal is active low at power on and whenever the diskette is removed. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN). Publication Release Date: March 1998 - 14 - W83877TF Version 0.61 ...
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... Drive Select A. When set to 0, this pin enables disk drive A. This is an open drain output. Drive Select B. When set to 0, this pin enables disk drive B. This is an open drain output. +5 power supply for the digital circuitry. Ground. Publication Release Date: March 1998 - 15 - W83877TF Version 0.61 ...
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... FDC FUNCTIONAL DESCRIPTION 2.1 W83877TF FDC The floppy disk controller of the W83877TF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to data rate 1 M bits/sec ...
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... A single command puts the FDC into perpendicular mode. All other commands operate as they normally do. The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. Publication Release Date: March 1998 - 17 - W83877TF Version 0.61 ...
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... Tape Drive The W83877TF supports standard tape drives (1 Mbps, 500 Kbps, 250 Kbps) and new fast tape drive (2M bps). 2.1.7 FDC Core The W83877TF FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor ...
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... HDS DS1 Publication Release Date: March 1998 - 19 - W83877TF D0 REMARKS 0 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Version 0.61 ...
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... HDS DS1 Publication Release Date: March 1998 - 20 - W83877TF D0 REMARKS 0 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Version 0.61 ...
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... HDS DS1 Publication Release Date: March 1998 - 21 - W83877TF D0 REMARKS 0 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after ...
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... HDS DS1 HDS DS1 - 22 - W83877TF D0 REMARKS 1 0 Command codes DS0 The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed D0 REMARKS 1 0 Command codes ...
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... HDS DS1 Publication Release Date: March 1998 - 23 - W83877TF D0 REMARKS 0 Command codes 0 Enhanced controller D0 REMARKS 1 Command codes DS0 Sector ID information prior to Command execution Data transfer between the FDD and system Status information after Command execution ...
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... HDS DS1 Publication Release Date: March 1998 - 24 - W83877TF D0 REMARKS 1 Command codes DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Version 0.61 ...
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... DS1 W83877TF D0 REMARKS 0 1 Command codes DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution D0 REMARKS 1 1 Command codes DS0 Head retracted to Track 0 Interrupt D0 REMARKS ...
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... FIFOTHR ----| EFIFO POLL HDS DS1 Publication Release Date: March 1998 - 26 - W83877TF D0 REMARKS 1 Command codes D0 REMARKS 1 Command codes DS0 Head positioned over proper cylinder on diskette D0 REMARKS 1 Configure information 0 Internal registers written D0 REMARKS 1 Command codes DS0 ...
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... LOCK HDS DS1 W83877TF D0 REMARKS 0 Registers placed in FIFO D0 REMARKS 1 0 Command code REMARKS 0 0 Command code REMARKS 0 0 Command code DS0 Status information about disk drive D0 REMARKS ...
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... Register Descriptions There are several status, data, and control registers in W83877TF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 ...
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... This bit indicates the complement of latched STEP output. TRAK0 (Bit 4): This bit indicates the complement of TRAK0 input. HEAD (Bit 3): This bit indicates the value of HEAD output. 0 side 1 1 side DIR WP INDEX HEAD TRAK0 STEP F/F DRQ INIT PENDING Publication Release Date: March 1998 - 29 - W83877TF Version 0.61 ...
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... MOT EN A (Bit 0) This bit indicates the complement of the MOA output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows MOT EN A MOT RDATA Toggle WDATA Toggle Drive SEL0 - 30 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR pin. The bit definitions are as follows DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 - 31 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... Motor Enable D. Motor D on when active high Tape sel 0 Tape sel Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 - 32 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET - 33 - W83877TF None Publication Release Date: March 1998 Version 0.61 ...
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... CR2D and the data rate table for individual data rates setting. PRECOMPENSATION DELAY 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 125 nS 125 nS 125 nS 41. W83877TF 2 Mbps Tape drive Default Delays 20.8nS 41.17nS 62.5nS 83.3nS 104.2nS 125.00nS 0.00nS (disabled) Publication Release Date: March 1998 Version 0.61 ...
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... This register stores data, commands, and parameters and provides diskette-drive status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83877TF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
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... US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 WP Write Protected FT Fault Reserved for the hard disk controller x During a read of this register, these bits are in tri-state DSKCHG - 36 - W83877TF RY Ready Publication Release Date: March 1998 Version 0.61 ...
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... DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC W83877TF HIGH DENS DRATE0 DRATE1 DSKCHG DRATE0 DRATE1 NOPREC DMAEN DSKCHG Publication Release Date: March 1998 Version 0.61 ...
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... This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC Reserved - 38 - W83877TF 0 DRATE0 DRATE1 DRATE0 DRATE1 NOPREC Publication Release Date: March 1998 Version 0.61 ...
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... The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16- byte FIFOs for both receive and transmit mode. Publication Release Date: March 1998 - 39 - W83877TF Version 0.61 ...
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... W83877TF Data Sheet Revision History Pages Dates 1 n.a. 03/20/97 2 n.a. 05/20/97 3 1,8,9,63,65, 03/20/98 78,80,104- 107,116,118, 119,133 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. ...
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... FEATURES ..........................................................................................................................2 PIN CONFIGURATION......................................................................................................4 1.0 PIN DESCRIPTION ........................................................................................................................5 1.1 HOST INTERFACE .........................................................................................................................5 1.2 SERIAL PORT INTERFACE ...........................................................................................................7 1.3 MULTI-MODE PARALLEL PORT ..................................................................................................8 1.4 FDC INTERFACE..........................................................................................................................14 2.0 FDC FUNCTIONAL DESCRIPTION........................................................................16 2.1 W83877TF FDC .............................................................................................................................16 2.2 REGISTER DESCRIPTIONS .........................................................................................................28 3.0 UART PORT................................................................................................................39 3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)..................39 3.2 REGISTER ADDRESS...................................................................................................................40 4.0 PARALLEL PORT.....................................................................................................49 4.1 PRINTER INTERFACE LOGIC .....................................................................................................49 4.2 ENHANCED PARALLEL PORT (EPP) .........................................................................................51 4.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT ...
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... UART/PARALLEL....................................................................................................................... 138 10.3 PARALLEL PORT ....................................................................................................................... 140 11.0 APPLICATION CIRCUITS....................................................................................146 11.1 PARALLEL PORT EXTENSION FDD ........................................................................................ 146 11.2 PARALLEL PORT EXTENSION 2FDD....................................................................................... 147 11.3 FOUR FDD MODE...................................................................................................................... 147 12.0 ORDERING INFORMATION ...............................................................................148 13.0 HOW TO READ THE TOP MARKING ...............................................................148 14.0 PACKAGE DIMENSIONS .....................................................................................149 W83877TF Publication Release Date: May 1997 - II - Preliminary Version 0.60 ...
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... Printer Interface Logic The parallel port of the W83877TF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83877TF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), and Extension 2FDD mode (EXT2FDD) on the parallel port ...
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... TABLE 4-1-B Parallel Port Connector and Pin Definition for EXTFDD and EXT2FDD Modes HOST PIN NUMBER CONNECTOR OF W83877TF PIN SPP PIN ATTRIBUTE ATTRIBUTE O nSTB --- ...
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... EPP address port (R/W) 0 EPP data port 0 (R/W) 1 EPP data port 1 (R/W) 0 EPP data port 2 (R/W) 1 EPP data port 2 (R/ W83877TF NOTE TMOUT ERROR SLCT PE ACK BUSY Publication Release Date: March 1998 Version 0. ...
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... Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR Publication Release Date: March 1998 - 52 - W83877TF Version 0.61 ...
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... CPU auses an EPP address write cycle to be performed, and the W83877TF 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 ...
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... PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 EPP DESCRIPTION Publication Release Date: March 1998 - 54 - W83877TF PD2 PD1 PD0 1 1 TMOUT INIT AUTOFD STROBE INIT AUTOFD STROBE PD2 PD1 PD0 PD2 ...
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... Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte repeated. The hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. W83877TF Publication Release Date: March 1998 - 55 - Version 0.61 ...
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... ECP FIFO (Address) R All Status Register R/W All Control Register R/W 010 Parallel Port Data FIFO R/W 011 ECP FIFO (DATA) R/W 110 Test FIFO R 111 Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register DESCRIPTION Publication Release Date: March 1998 - 56 - W83877TF FUNCTION Version 0.61 ...
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... Bit 2-0: These three bits are not implemented and are always logic one during a read Address/RLE W83877TF PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Address or RLE nFault Select PError nAck nBusy Publication Release Date: March 1998 Version 0.61 ...
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... When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system W83877TF Strobe Autofd nInit Select In AckInt En Direction Publication Release Date: March 1998 Version 0.61 ...
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... IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits are at high level during a read and can be written IRQ resource - 59 - W83877TF IRQx 0 IRQx 1 IRQx 2 intrValue compress . Publication Release Date: March 1998 Version 0.61 ...
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... Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will be generated and this bit is written from Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally Empty Full Service Intr DMA En nErrIntr En MODE MODE MODE - 60 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... All FIFOs use one common 16-byte FIFO PD5 PD4 PD3 PError Select nFault Directio ackIntEn SelectIn nErrIntrEn dmaEn serviceIntr Publication Release Date: March 1998 - 61 - W83877TF NOTE PD2 PD1 PD0 nInit autofd strobe ...
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... ECP Mode. O This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. O This signal is always deasserted in ECP mode W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... PeriphAck is low. The most significant bit of the command is always zero. Data Compression The W83877TF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that the odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
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... I/O will empty or fill the FIFO using the appropriate direction and mode. 4.4 Extension FDD Mode (EXTFDD) In this mode, the W83877TF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1 ...
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... PLUG AND PLAY CONFIGURATION A powerful new plug-and-play function has been built into the W83877TF to help simplify the task of setting up a computer environment. With appropriate support from BIOS manufacturers, the system designer can freely allocate Winbond I/O devices (i.e., the FDC, PRT and UART ) in the PC's I/O space (100H - 3FFH) ...
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... SERIAL IRQ W83877TF supports a serial IRQ scheme. This allow a signal line to be used to report the legacy ISA interrupt requests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is transferred on the IRQSER signal, one cycle consisting of three frames types: a start frame, several IRQ/Data frame, and one Stop frame ...
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... If the corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device left the IRQSER tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 7-1. W83877TF Publication Release Date: March 1998 - 67 - Version 0.61 ...
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... Start IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK INTA INTB INTC INTD Unassigned - 68 - W83877TF Publication Release Date: March 1998 ...
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... MR = 1). A warm reset will not affect the configuration registers. 8.1 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83877TF enters the default operating mode. Before the W83877TF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers ...
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... LIH I LIL LIH I LIL LIH I LIL - 129 - W83877TF UNIT UNI CONDITIONS V DD +0 0.8 V +0 ...
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... LIL V 0.3xV IL V 0.7xV +10 LIH I -10 LIL V 1.3 1.5 1 3..2 3 +10 LIH I -10 LIL - 130 - W83877TF UNIT CONDITIONS - ...
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... MCY 260/430 AA /510 131 - W83877TF TYP. MAX. UNIT (NOTE 360/570 nS /675 360/570 nS /675 Publication Release Date: March 1998 Version 0.61 ...
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... T 135/220 TC /260 T 1.8/3/3. RST T 0.5/0.9 IDX T 1.0/1.6 DST T 24/40/48 STD T 6.8/11.5 STP /13.8 T Note 100/185 WDD /225 T 100/138 WPC /225 - 132 - W83877TF TYP. MAX. (NOTE 1) 6/12 /20/24 5 /1.0 /2.0 7/11.7 7.2/11.9 /14 /14.2 Note 2 Note 2 125/210 150/235 /250 /275 125/210 150/235 /250 /275 Publication Release Date: March 1998 Version 0.61 UNIT ...
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... IR T 100 pF Loading MWO T SIM T RIM T 100 pF Loading IAD T 100 pF Loading IID N 100 pF Loading SYM. MIN 200 t5 Publication Release Date: March 1998 - 133 - W83877TF MIN. MAX. UNIT 9/16 Baud Rate 1 S 1/16 8/16 Baud Rate 175 nS 9/16 16/16 Baud Rate 1/2 Baud Rate 250 nS 200 nS ...
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... Publication Release Date: March 1998 - 134 - W83877TF UNIT 160 185 nS 190 180 190 ...
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... Publication Release Date: March 1998 - 135 - W83877TF UNIT 160 185 nS 185 210 nS 190 Version 0 ...
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... SYMBOL MIN. MAX 200 t6 80 200 Publication Release Date: March 1998 - 136 - W83877TF UNIT UNIT UNIT Version 0.61 ...
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... TMW (IOW) TMR (IOR) TRA TRR TDH TDF INDEX TR TWA TWW TWD TDW TWI DIR TMCY TAA STEP - 137 - W83877TF Write Date WD TWDD Index TIDX TIDX Terminal Count TC TTC Reset RESET TRST Drive Seek operation TSTP TDST TSTD TSC Publication Release Date: March 1998 ...
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... SERIAL OUT (SOUT) THRS IRQ3 or IRQ4 THR IOW (WRITE THR) IOR (READ TIR) Receiver Timing STAR DATA BITS (5-8) PARITY Transmitter Timing STAR DATA (5-8) PARITY THR TSI - 138 - W83877TF STOP TSINT TRINT STAR STOP (1-2) TSTI TIR Publication Release Date: March 1998 Version 0.61 ...
Page 84
... Printer Interrupt Timing ¢x ¢x ¢x ¢ ¢x ¡ ö TLAD ¢x ¢x ¢x ¢x ¢x ¢ ¢x ¢x - 139 - W83877TF ¢x ¢x ¢x ¡ ÷ ¡ ö TMWO ¢x ¢ ¢x ¢x ¢x ¢x ¢ ¡ ö TSIM ¢x ¢x ¢ ...
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... PARALLEL PORT 10.3.1 Parallel Port Timing IOW INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ Publication Release Date: March 1998 - 140 - W83877TF t3 t4 Version 0.61 ...
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... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t22 t23 t24 ADDRSTB DATASTB WAIT t18 t21 t25 t27 t26 - 141 - W83877TF t15 t19 t20 t28 Publication Release Date: March 1998 Version 0.61 ...
Page 87
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR t10 t11 t13 t15 t16 t17 t18 t19 t20 - 142 - W83877TF t12 t14 t21 Publication Release Date: March 1998 Version 0.61 ...
Page 88
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 ADDRSTB t24 DATASTB WAIT t18 t25 t26 t27 Publication Release Date: March 1998 - 143 - W83877TF t15 t19 t20 t28 Version 0.61 ...
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... IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT 10.3.6 Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t10 t11 t13 t15 t16 t17 t18 t19 t20 t1 t2 > >| t6 >| - 144 - W83877TF t22 t22 t4 >| t3 >| t5 >| Publication Release Date: March 1998 Version 0.61 ...
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... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY 10.3.8 ECP Parallel Port Reverse Timing PD<0:7> nACK nAUTOFD 145 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
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... Parallel Port Extension FDD Mode Connection Diagram DCH2 34 HEAD2 32 RDD2 30 WP2 28 TRK02 26 WE2 24 WD2 22 STEP2 20 DIR2 18 MOB2 16 14 DSB2 12 10 IDX2 RWC2 2 EXT FDC Publication Release Date: March 1998 - 146 - W83877TF JP 13A Version 0.61 ...
Page 92
... Parallel Port Extension 2FDD Connection Diagram 11.3 Four FDD Mode W83777F DSA DSB MOA MOB JP13 74LS139 G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 147 - W83877TF JP 13A DCH2 34 33 HEAD2 32 31 RDD2 30 29 WP2 28 27 TRK02 26 25 WE2 24 23 WD2 22 21 STEP2 ...
Page 93
... Example: The top marking of W83977TF-A inbond W83877TF 719AB27039520 1st line: Winbond logo 2nd line: the type number: W83877TF 3rd line: tracking code 719: packages made in '97, week 19 A: assembly house ID; A means ASE, S means SPIL....etc C: IC revision; B means version B, C means version C ...
Page 94
... PACKAGE DIMENSIONS W83877TF (100-pin QFP 100 See Detail F y Seating Plane Detail F - 149 - W83877TF Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.130 3.30 A 0.004 0. 0.107 0.112 ...
Page 95
... Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 - 150 - W83877TF Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.05 0.10 A 0.002 0.004 0.006 ...
Page 96
... EFDR. The bit definitions for CR0 are as follows Bit 7-bit 4: Reserved. PRTMOD1 PRTMOD0 (Bit 3, 2): These two bits and PRTMOD2 (CR9 bit 7) determine the parallel port mode of the W83877TF (as shown in the following Table 8-1). Table 8-1 PRTMODS2 PRTMODS1 (BIT 7 OF CR9) ...
Page 97
... Bit 1: Reserved. IPD (Bit 0): This bit is used to select the W83877TF's legacy power-down functions. When the bit 0 is set to 1, the W83877TF will stop its clock internally and enter power-down (IPD) mode immediately. The W83877TF will not leave the power-down mode until either a system power-on reset from the MR pin or this bit is reset program the chip back to power-on state ...
Page 98
... This bit selects the clock divide rate of UARTB. 0 Disables MIDI support, UARTB clock = 24 MHz divided by 13 (default) 1 Enables MIDI support, UARTB clock = 24 MHz divided SUBMIDI SUAMIDI reserved reserved reserved EPPVER reserved reserved Publication Release Date: March 1998 - 72 - W83877TF Version 0.61 ...
Page 99
... The output pins of UARTB will not be tri-stated when UARTB is in power-down mode. 1 The output pins of UARTB will be tri-stated when UARTB is in power-down mode URBTRI URATRI reserved PRTTRI URBPWD URAPWD reserved PRTPWD - 73 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
Page 100
... DSA , DSB , MOA and MOB output pins are encoded as show in Table 8-3 to select four drives ECPFTHR0 ECPFTHR1 ECPFTHR2 ECPFTHR3 reserved reserved reserved reserved reserved FDCTRI reserved FDCPWD FIPURDWM SEL4FDD reserved reserved - 74 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
Page 101
... MOB MOA Bit 1 Bit W83877TF DRIVE DSB DSA SELECTED FDD FDD DRIVE DSB DSA SELECTED FDD FDD ...
Page 102
... RWC = 0, selects 1.2 MB high-density FDD. 10 RWC = 1, selects 1.44 MB high-density FDD. 11 Don't care RWC, selects 720 KB double-density FDD FDD A type 0 FDD A type 1 FDD B type 0 FDD B type 1 FDD C type 0 FDD C type 1 FDD D type 0 FDD D type W83877TF Publication Release Date: March 1998 Version 0.61 ...
Page 103
... KB double-density FDD Floppy Boot Drive 0 Floppy Boot Drive 1 Media ID 0 Media ID 1 SWWP DISFDDWR reserved reserved - 77 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
Page 104
... This bit and PRTMODS1, PRTMODS0 (bits CR0) select the operating mode of the W83877TF. Refer to the descriptions of CR0. LOCKREG (Bit 6): This bit enables or disables the reading and writing of all configuration registers. 0 Enables the reading and writing of CR0-CR45 1 Disables the reading and writing of CR0-CR45 (locks W83877TF extension functions) default = 0CH ...
Page 105
... CHIP ID 3, CHIP ID 2, CHIP ID 1, CHIP ID 0 (Bit 3-bit 0): These four bits are read-only bits that contain chip identification information. The value is 0CH for W83877TF during a read. 8.2.11 Configuration Register A (CR0A), When the device is in Extended Function mode and EFIR is 0AH, the CRA register can be accessed through EFDR ...
Page 106
... FDD interface signals are active low 1 FDD interface signals are active high DRV2EN (Bit 0): PS/2 mode only When this bit is a logic 0, this indicates that a second drive is installed and is reflected in status register A. INTERFACE Model 30 mode PS/2 mode AT mode AT mode Publication Release Date: March 1998 - 80 - W83877TF Version 0.61 ...
Page 107
... TX2INV RX2INV reserved URIRSEL reserved HEFERE TURB TURA address and value write 88H to the location 250H write 89H to the location 250H (default) write 86H to the location 3F0H twice write 87H to the location 3F0H twice Publication Release Date: March 1998 - 81 - W83877TF Version 0.61 ...
Page 108
... IRMODE0 (Bit 0): IR function mode selection bit IRMODE0 IRMODE1 IRMODE2 HDUPLX SIRRX0 SIRRX1 SIRTX0 SIRTX1 IRTX output on pin disabled IRTX1 (pin 43) IRTX2 (pin 95) disabled IRRX input on pin disabled IRRX1 (pin 42) IRRX2 (pin 94) disabled Publication Release Date: March 1998 - 82 - W83877TF Version 0.61 ...
Page 109
... ASK_IR 0 MUX MUX 0 IRMODE2 IRMODE1 (CRD.bit2) (CRD.bit1) IRDA MUX 1 MUX IRMODE2 (CRD.bit2) 1 URIRSEL (CRC,bit3 W83877TF IRRX high Demodulation into SINB Demodulation into SINB routed to SINB routed to SINB Demodulation into SINB Demodulation into SINB IRRX1 SIN2 01 00 +5V IRRX2 NCS0 (default) 10 MUX ...
Page 110
... GIO0AD3 GIO0AD4 GIO0AD5 GIO0AD6 GIO0AD7 GIO0AD8 GIO0AD9 GIO0AD10 reserved reserved reserved G0CADM0 G0CADM1 GIOP0 pin compare GIO0AD10-GIO0AD0 with SA10-SA0 compare GIO0AD10-GIO0AD1 with SA10-SA1 compare GIO0AD10-GIO0AD2 with SA10-SA2 compare GIO0AD10-GIO0AD3 with SA10-SA3 Publication Release Date: March 1998 - 84 - W83877TF Version 0.61 ...
Page 111
... GIO1AD3 GIO1AD4 GIO1AD5 GIO1AD6 GIO1AD7 GIO1AD8 GIO1AD9 GIO1AD10 reserved reserved reserved G1CADM0 G1CADM1 GIOP1 pin compare GIO1AD10-GIO1AD0 with SA10-SA0 compare GIO1AD10-GIO1AD1 with SA10-SA1 compare GIO1AD10-GIO1AD2 with SA10-SA2 compare GIO1AD10-GIO1AD3 with SA10-SA3 Publication Release Date: March 1998 - 85 - W83877TF Version 0.61 ...
Page 112
... GIO0AD10-0), the value of SD0 will be present on GIOP0 When (AEN = L) AND (NIOR = L) AND (SA10 GIO0AD10-0), the value of GIOP0 will be present on SD0 Chip Select pin, the pin will be active at (AEN = L) AND (SA10-0 = GIO0AD10-0) OR (NIOR = L) OR (NIOW = L) Publication Release Date: March 1998 - 86 - W83877TF Version 0.61 ...
Page 113
... When the device is in Extended Function mode and EFIR is 15H, the CR15 register can be accessed through EFDR. The bit definitions are as follows W83877TF GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0CSH GIOP0MD0 GIOP0MD1 GIOP0MD2 Publication Release Date: March 1998 Version 0.61 ...
Page 114
... GIO1AD10-0), the value of SD1 will be present on GIOP1 When (AEN = L) AND (NIOR = L) AND (SA10 GIO1AD10-0), the value of GIOP1 will be present on SD1 Chip Select pin, the pin will be active at (AEN = L) AND (SA10-0 = GIO1AD10-0) OR (NIOR = L) OR (NIOW = L) Publication Release Date: March 1998 - 88 - W83877TF Version 0.61 ...
Page 115
... Bit 3: Reserved. PNPCVS (bit 2): 0 PnP-related registers (CR20, CR23-29) reset to be all 0s. 1 default settings for these registers. default = 04H W83877TF SD1, inverse HEFRAS reserved PNPCVS reserved G0IQSEL G1IQSEL reserved reserved Publication Release Date: March 1998 Version 0.61 ...
Page 116
... EFDR. The bit definitions are as follows: 7 Bit 7-bit 5: Reserved. PNPCVS = 0 FCH 00H DEH 00H FEH 00H BEH 00H 23H 00H 05H 00H 43H 00H 60H 00H DSUBLGRQ DSUALGRQ DSPRLGRQ DSFDLGRQ PRIRQOD reserved reserved reserved - 90 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
Page 117
... When the device is in Extended Function mode and EFIR is 18H, the CR18 register can be accessed through EFDR. The bit definitions are as follows SHARA SHARB SHARC SHARD SHARE SHARF SHARG SHARH Publication Release Date: March 1998 - 91 - W83877TF Version 0.61 ...
Page 118
... IRQ_C in the IRQ sharing mode. SHARB(Bit 1): 0 pin IRQ_B in the legacy ISA IRQ mode. 1 pin IRQ_B in the IRQ sharing mode. SHARA (Bit 0): 0 pin IRQ_A in the legacy ISA IRQ mode. 1 pin IRQ_A in the IRQ sharing mode. W83877TF Publication Release Date: March 1998 - 92 - Version 0.61 ...
Page 119
... EFDR. Default = FCH if CR16 bit default = 00H if CR16 bit The bit definitions are as follows FASTB FASTA reserved reserved reserved reserved reserved reserved reserved reserved FDCAD2 FDCAD3 FDCAD4 FDCAD5 FDCAD6 FDCAD7 Publication Release Date: March 1998 - 93 - W83877TF Version 0.61 ...
Page 120
... NCS = 0 and A10 = 0 are required to access the UART A registers. A[2:0] are don't-care conditions PRTAD0 PRTAD1 PRTAD2 PRTAD3 PRTAD4 PRTAD5 PRTAD6 PRTAD7 reserved URAAD1 URAAD2 URAAD3 URAAD4 URAAD5 URAAD6 URAAD7 Publication Release Date: March 1998 - 94 - W83877TF Version 0.61 ...
Page 121
... FDCDQS3-FDCDQS0 (Bit 7-bit 4): Allocate DMA resource for FDC. PRTDQS3-PRTDQS0 (Bit 3-bit 0): Allocate DMA resource for PRT W83877TF reserved URBAD1 URBAD2 URBAD3 URBAD4 URBAD5 URBAD6 URBAD7 PRTDQS0 PRTDQS1 PRTDQS2 PRTDQS3 FDCDQS0 FDCDQS1 FDCDQS2 FDCDQS3 Publication Release Date: March 1998 ...
Page 122
... PRTIQS3-PRTIQS0 (Bit 3-bit 0): Select IRQ resource for the parallel port. Any unselected IRQ pin is in tri-state. DMA selected None DMA_A DMA_B DMA_C PRTIQS0 PRTIQS1 PRTIQS2 PRTIQS3 reserved ECPIRQx0 ECPIRQx1 ECPIRQx2 IRQ resource Publication Release Date: March 1998 - 96 - W83877TF Version 0.61 ...
Page 123
... None IRQ_A IRQ_B IRQ_C IRQ_D IRQ_E IRQ_F IRQ_G IRQ_H None IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Publication Release Date: March 1998 - 97 - W83877TF Version 0.61 ...
Page 124
... EFDR. The bit definitions are as follows: 7 Bit 7 - bit 3 : Reserved W83877TF URBIQS0 URBIQS1 URBIQS2 URBIQS3 URAIQS0 URAIQS1 URAIQS2 URAIQS3 0 IQNIQS0 IQNIQS1 IQNIQS2 IQNIQS3 FDCIQS0 FDCIQS1 FDCIQS2 FDCIQS3 reserved reserved CLKINSEL reserved reserved reserved ...
Page 125
... DRTA1, DRTA0 (Bit 1 - bit 0): These two bits combining with data rate selection bits in Date Rate Register select the operational data rate for FDD A as follows DRTA0 DRTA1 DIS_PRECOMP0 DRTB0 DRTB1 DIS_PRECOMP1 reserved reserved - 99 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
Page 126
... W83877TF operational data rate MFM FM 1M --- 500K 250K 300K 150K 250K 125K 1M --- 500K 250K 500K 250K 250K 125K 1M --- 500K 250K 2M --- 250K 125K reserved reserved IRQMODS ...
Page 127
... Bit 3: Reserved. Mapped IRQ pin None IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 Publication Release Date: March 1998 - 101 - W83877TF Version 0.61 ...
Page 128
... IRQMODS (Bit 2): IRQ mode selection. The W83877TF supports: (1) legacy ISA IRQ mode or ISA IRQ sharing mode. (2) Serial IRQ mode used in the PCI bus. In the legacy ISA IRQ sharing mode, the selected IRQ pin for the device's IRQ is defined in the configuration registers CR27 - CR29. In the ISA IRQ sharing mode, configuration register CR18 indicates which IRQ pin is in the IRQ sharing mode ...
Page 129
... W83877TF reserved reserved PM1AD2 PM1AD3 PM1AD4 PM1AD5 PM1AD6 PM1AD7 reserved GPEAD1 GPEAD2 GPEAD3 GPEAD4 GPEAD5 GPEAD6 GPEAD7 Publication Release Date: March 1998 Version 0.61 ...
Page 130
... EFDR. The bit definitions are as follows ,i.e., 100H ~ 3F8H, where bit 0 of the base address URACNT0 URACNT1 URACNT2 URACNT3 URACNT4 URACNT5 URACNT6 URACNT7 URBCNT0 URBCNT1 URBCNT2 URBCNT3 URBCNT4 URBCNT5 URBCNT6 URBCNT7 Publication Release Date: March 1998 - 104 - W83877TF Version 0.61 ...
Page 131
... FDC is enabled, that is, CHIPPME=1 (CR32 bit 7) and FDCPME=1 (CR32 bit 2), (2). If the register is set to 00H, FDC will remain in the current state(working or sleeping FDCCNT0 FDCCNT1 FDCCNT2 FDCCNT3 FDCCNT4 FDCCNT5 FDCCNT6 FDCCNT7 Publication Release Date: March 1998 - 105 - W83877TF Version 0.61 ...
Page 132
... The time resolution of this register value is minute or second, which is defined by the TMIN_SEL bit of CR3A. Note that (1). this register is valid when the CHIPPME = 1 (CR32 bit 7), and (2) If the register is set to 00H, W83877TF chip will remain in the current state(working or sleeping). ...
Page 133
... IRQSER pin. 1 enable the pull up of IRQSER pin. 8.2.46 Configuration Register 3B (CR3B), default=00H Reserved for testing. Should be kept all 0' 107 - W83877TF UPULLEN SMI_EN reserved reserved reserved TMIN_SEL reserved reserved Publication Release Date: March 1998 Version 0.61 ...
Page 134
... These bits indicate that the individual device's idle timer expires due to no I/O access, IRQ, and external input to the device respectively. These 4 bits are controlled by the printer port, FDC, UART A, and UART B power down machines individually. The bits are set/cleared by W83877TF automatically. Writing a 1 can also clear this bit, and writing a 0 has no effect. ...
Page 135
... The device's idle timer reloads the initial count value from CR35-CR39, depending on which device wakes up. These 4 bits are controlled by the printer port, FDC, UART A, and UART B power down machines individually. The bits are set/cleared by W83877TF automatically. Writing a 1 can also clear this bit, and writing a 0 has no effect. ...
Page 136
... Configuration Register 44 (CR44), default=00H When the device is in Extended Function mode and EFIR is 44H, the CR44 register can be accessed through EFDR. This register is reserved URBIRQSTS URAIRQSTS FDCIRQSTS PRTIRQSTS reserved reserved reserved reserved Publication Release Date: March 1998 - 110 - W83877TF Version 0.61 ...
Page 137
... URBIRQEN (Bit 0): 0 disable the generation of an SMI interrupt due to the UART B's IRQ. 1 enable the generation of an SMI interrupt due to the UART B's IRQ URBIRQEN URAIRQEN FDCIRQEN PRTIRQEN reserved reserved reserved reserved Publication Release Date: March 1998 - 111 - W83877TF or Version 0.61 ...
Page 138
... FDCCNT4 PRTCNT6 PRTCNT5 PRTCNT4 GSBCNT6 GSBCNT5 GSBCNT4 0 TMIN_SEL 112 - W83877TF PRTMODS1 PRTMODS0 SUAMIDI PRTTRI 0 URATRI ECPFTHR3 ECPFTHR2 ECPFTHR1 FDCPWD 0 FDCTRI FDD B T1 FDD B T0 FDD A T1 MEDIA 1 ...
Page 139
... ACPI Registers Features W83877TF supports both the ACPI and legacy power management's. The switch logic of the power management block generates an SMI interrupt in the legacy mode and an SCI interrupt in the ACPI mode. For the legacy mode, the SMI_EN bit is used set, it routes the power management events from the SMI interrupt logic to the SMI output pin ...
Page 140
... Writing GBL_RLS has no effect. Writing BIOS_STS clears it to logic 0 and also clears GBL_RLS to logic 0; writing BIOS_STS has no effect. clear GBL_STS set To SCI Logic clear BIOS_STS set To SMI Logic clear BM_STS set To SCI Logic Publication Release Date: March 1998 - 114 - W83877TF Version 0.61 ...
Page 141
... Except for some special status bits, every status bit has an associated enable bit in the same bit position in the enable register. Those TMR_STS 24 bit counter Bits (23-0) 24 TMR_EN TMR_VAL Publication Release Date: March 1998 - 115 - W83877TF To SCI Logic Version 0.61 ...
Page 142
... Reserved. These bits always return a value of zero. to 11,1111,0000 ,i.e., 100H ~ 3F0H, where bit 1 and bit 11,1111,1000 ,i.e., 100H ~ 3F8H, where bit 0 of the base Description - 116 - W83877TF TMR_STS Reserved Reserved Reserved BM_STS GBL_STS Reserved Reserved Publication Release Date: March 1998 Version 0.61 ...
Page 143
... System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits Reserved Reserved Reserved Reserved Reserved Reserved Reserved WAK_STS Description TMR_EN Reserved Reserved Reserved GBL_EN Reserved Reserved Reserved Publication Release Date: March 1998 - 117 - W83877TF Version 0.61 ...
Page 144
... Reserved. These bits always return a value of zero. 8.4.5 Power Management 1 Control Register 1 (PM1CTL1) Register Location: <CR33>+4H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date: March 1998 - 118 - W83877TF Version 0.61 ...
Page 145
... Name 0-7 Reserved Reserved. These bits always return a value of zero SCI_EN BM_RLD GBL_RLD Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date: March 1998 - 119 - W83877TF Version 0.61 ...
Page 146
... Name 0-7 Reserved Reserved. These bits always return a value of zero Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date: March 1998 - 120 - W83877TF Version 0.61 ...
Page 147
... System I/O Space Default Value: 00h Attribute: Read only Size: 8 bits TMR_VAL0 TMR_VAL1 TMR_VAL2 TMR_VAL3 TMR_VAL4 TMR_VAL5 TMR_VAL6 TMR_VAL7 Description TMR_VAL8 TMR_VAL9 TMR_VAL10 TMR_VAL11 TMR_VAL12 TMR_VAL13 TMR_VAL14 TMR_VAL15 Publication Release Date: March 1998 - 121 - W83877TF Version 0.61 ...
Page 148
... If the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Description TMR_VAL16 TMR_VAL17 TMR_VAL18 TMR_VAL19 TMR_VAL20 TMR_VAL21 TMR_VAL22 TMR_VAL23 Description Publication Release Date: March 1998 - 122 - W83877TF Version 0.61 ...
Page 149
... PRT SCI status, which is set by the printer port IRQ. 4-7 Reserved Reserved Description Description - 123 - W83877TF Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved URBSCISTS URASCISTS FDCSCISTS PRTSCISTS Reserved Reserved Reserved Reserved Publication Release Date: March 1998 Version 0.61 ...
Page 150
... SCI logic output = (URBSCIEN and URBSCISTS) or (URASCIEN and URASCISTS) or (FDCSCIEN and FDCSCISTS) or (PRTSCIEN and PRTSCISTS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description 124 - W83877TF URBSCIEN URASCIEN FDCSCIEN PRTSCIEN Reserved Reserved Reserved Reserved Publication Release Date: March 1998 Version 0.61 ...
Page 151
... Reserved. These bits always return a value of zero. 8.4.17 General Purpose Event 1 Status Register 1 (GP1STS1) Register Location: <CR34>+4H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description - 125 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
Page 152
... System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits BIOS_STS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description - 126 - W83877TF Publication Release Date: March 1998 Version 0.61 ...
Page 153
... BM_STS. Writing a 0 has no effect. Writing BM_STS clears BM_STS and also clears BM_CNTRL. 2-7 Reserved Reserved Description BIOS_RLS BM_CNTRL Reserved Reserved Reserved Reserved Reserved Reserved Description - 127 - W83877TF BIOS_EN TMR_ON Reserved Reserved Reserved Reserved Reserved Reserved Publication Release Date: March 1998 Version 0.61 ...
Page 154
... 128 - W83877TF GBL_RLS BM_RLD TMR_VAL3 TMR_VAL2 TMR_VAL1 TMR_VAL11 TMR_VAL10 TMR_VAL9 TMR_VAL19 TMR_VAL18 ...