CXD1199AQ Sony, CXD1199AQ Datasheet
CXD1199AQ
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CXD1199AQ Summary of contents
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... CD-ROM DECODER For the availability of this product, please contact the sales office. Description The CXD1199AQ is a CD-ROM decoder LSI with a built-in ADPCM decoder. Features • Supports CD-ROM, CD-I and CD-ROM XA formats • Real-time error correction • Supports double speed playback • Connectable with standard SRAM M-bits (128 K-byte) • ...
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... Block Diagram – MDB0-7, P XMWR XMOE MA0-16 —2— CXD1199AQ TD0-7 EMP A0-A4 XINT XWR XRD XCS D0-7 ...
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... Interrupt request negative logic signal to host; open drain output Host strobe negative logic signal to read this IC internal register Power supply (+5 V) GND Host strobe negative logic signal to read this IC internal register Host data bus Host data bus Host data bus Host data bus Host data bus —3— CXD1199AQ ...
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... Buffer memory address Buffer memory address Buffer memory address Buffer memory output enable negative logic signal GND Buffer memory write enable negative logic signal Buffer memory data bus Buffer memory data bus Buffer memory data bus Buffer memory data bus —4— CXD1199AQ ...
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... Error flag (C2 pointer) positive logic signal from CD DSP Emphasis ON positive logic signal from CD DSP Reset negative logic signal GND Data signal to DAC (D/A converter) LR clock signal to DAC Word clock signal to DAC Bit clock signal to DAC Mute positive logic signal Test I/O Test I/O Test I/O Test I/O Test I/O —5— CXD1199AQ ...
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... OZ state V 0.7 V IH4 V IL4 250 =–3 mA 0.5 V OH2 OL2 OL —6— CXD1199AQ =0 V, Topr=– °C) SS Typ. Max. Unit 0.4 V –200 –440 µA –100 –240 µ ...
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... OZ state V 0.7 V IH4 V IL4 1 =–1.3 mA 0.5 V OH2 =1.3 mA OL2 OL —7— CXD1199AQ =0 V, Topr=– °C) SS Typ. Max. Unit 0.3 V –50 –110 µA –25 –60 µ ...
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... All output pins except XTL2. 8. All input pins except 5, 6 and XTL1. 9. HINT 10. input : XTL1; output : XTL2 I/O capacitance Item Input pin Output pin I/O pin Symbol Min. Typ OUT C OUT —8— CXD1199AQ ( f=1 MHz Max. Unit ...
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... Min. Tsar 30 (70) Thar 20 (50) Tdrd Tfrd 0 Trr1 100 (150) Thaw Tww1 Tsdw Thdw Symbol Min. Tsaw 30 (70) Thaw 20 (50) Tsdw 40 (70) Thdw 10 (30) Tww1 50 (80) —9— CXD1199AQ Typ. Max. Unit (100 (25 Typ. Max. Unit ...
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... LRCK, C2PO setup time (for BCLK) LRCK, C2PO hold time (for BCLK) Tbck Tbck Tsb1 Thb1 Thb2 Tbck Tbck Tsb1 Thb1 Thb2 Symbol Min. Fbck Tbck 88 Tsb1 20 Thb1 20 Tsb2 20 Thb2 20 —10— CXD1199AQ Tsb2 Tsb2 Typ. Max. Unit 11.3 MHz ...
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... Min. Typ. Thsar 30 (70) Thhar 20 (50) Thdrd Thfrd 0 Thrd1 100 (150) Thhar Thww1 Thswd Thhwd Symbol Min. Typ. Thsar 30 (70) Thhar 20 (50) Thswd 40 (70) Thhwd 10 (30) Thww1 60 (100) —11— CXD1199AQ Max. Unit (100 (25 Max. Unit ...
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... Tdad Thww1 Thac Tsac Thswd2 Thhwd2 Symbol Min. Tdad Tdar Tsac 5 (20) Thac 0 (20) Thswd2 40 (70) Thhwd2 10 (30) Thww1 60 (100) —12— CXD1199AQ Tdar Typ. Max. Unit 45 (70 (70 (100 (25 Tdar Typ. Max. Unit 45 (70) ns ...
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... BCKO frequency BCKO pulse width DATO, WCO1, WCO2, LRCO setup time (for BCKO ) DATO, WCO1, WCO2, LRCO hold time (for BCKO ) Tbco Tbco Tsbo Thbo Thbo Symbol Min. Typ. Fbco 8.4672 Tbco 50 Tsbo 30 Thbo 30 —13— CXD1199AQ Tsbo Max. Unit MHz ...
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... Typ. Fmax 16.9344 Tw Twlx Tf Symbol Min. Typ. Twhx 20 Twhx Vihx V –1.0 DD Vihx Tr Tf Symbol Min. Typ. Fmck is 5 V± —14— CXD1199AQ Max. Unit MHz Vihx Vidx 0.9 Vdd/2 Vihx 0.1 Vilx Max. Unit 0 Max. Unit 33.3 MHz (23.4 with 3.5 V) ...
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... (sub CPU address : input) Address signal for selecting IC internal register from sub CPU. (5) XINT (sub CPU interrupt : output) Interrupt request negative logic signal to sub CPU. (6) XCS (chip select : input) IC select negative logic signal from sub CPU. resistance ; MDBP pin is left open —15— CXD1199AQ ...
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... The output format to DAC is shown in Fig.1-1. (1) BCKO (bit clock output : output) Bit clock output signal to D/A converter. (2) WCKO (word clock output : output) Word clock output signal to D/A converter. (3) LRCO (LR clock output : output) LR clock output signal to D/A converter. (4) DATO (data output : output) Data output signal to D/A converter. —16— CXD1199AQ ...
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... This pin is low when the IC has been reset by the host open drain output. (10) TD0 to 7 (test data input/output) The data pins for testing the IC. They are pulled open. 1-7. Power supply pins (12 pins pins ; GND: 8 pins DD standard resistor and are normally left —18— CXD1199AQ ...
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... Normally set below. Any change of each bit value in this register must be made in the decoder disable status. Table 2-1-1 shows the settings for bits when this IC is connected to Sony’s CD DSP. Figs. 2-1-1 (1) to (3) are input timing charts. 16 BCLKs/WCLK 24 BCLKs/WCLK 32 BCLKs/WCLK —19— CXD1199AQ ...
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... CDL40 Series L (48-bit slot mode) CDL40 Series L (64-bit slot mode) Table 2-1-1. DR VIF Register Settings DR VIF register bit6 bit5 bit4 bit3 bit2 lrck bedg bck1 bck0 lsb Fig. 2-1-1. ( Fig. 2-1-1. ( Fig. 2-1-1. (3) —21— CXD1199AQ Timing chart ...
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... High : 2 buffer surfaces for the sound map Low : 3 buffer surfaces for the sound map = 3.5 V. When XSLOW is low, erasure DD 9 BITRAM SRAM size “L” “H” “L” “H” “L” 128 Kw 8b “H” 128 Kw 9b —22— CXD1199AQ ...
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... When the CD-DA bit (bit 4) in the CHPCTL register set high, set the decoder to the disable or CD-DA mode. MODE1 MODE2, FORM1 MODE2, FORM2 DECMD0 “X” Decoder disable “X” Monitor-only mode “L” Write-only mode “H” Real-time correction mode “L” Repeat correction mode “H” CD-DA mode —23— CXD1199AQ ...
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... ENDLADR bit value. bit 6 : DECTOUT (decoder time out) The DECTOUT status is established when the sync mark is not detected even after 3 sectors (40 normal speed playback) have elapsed after the decoder has been set to the monitor-only, write-only or real-time correction mode. —24— CXD1199AQ ...
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... The CD DSP and this IC are synchronized when this bit is set high. Set the bit high by the sub CPU in the following cases: (1) After the DRVIF register has been set (2) After the DBLSPD bit (bit 1 of the CHPCTL register) has been set low. This bit is automatically set low when the CD DSP and this IC are synchronized. —25— CXD1199AQ ...
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... The sub CPU sets this number when data is transferred between the host and buffer memory by setting the DISHXFRC bit low. 2-1-14. HADR-L register 2-1-15. HADR-M register 2-1-16. HADR-H register The HADR (host address) register is for the head addresses of data transfer between the host and buffer memory. 2-1-17. DADRC-L register 2-1-18. DADRC-M register —26— CXD1199AQ ...
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... ADPMNT register bit 7 : RTADPEN (real-time ADPCM enable) The sub CPU sets this high to perform real-time ADPCM playback. bits The upper 7 bits (bits 16 to 10) of the sector head address are written into these bits to perform real-time ADPCM playback. —27— CXD1199AQ ...
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... CPU. The HCRISD bit value is not affected by soft resetting by the host. “Hard reset” means that the XRST pin is set low; “soft reset” means that the IC is reset by the sub CPU or host. —28— CXD1199AQ ...
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... Description Error(s) present in current sector (1), (2) or (3) applies: (1) EDC overlocked (2) Error corrected (3) Error(s) present in header byte with FORM2 (1) EDC overlocked or (3) Error(s) present in P parity byte No error(s) in current sector —29— CXD1199AQ ...
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... CMADR (current minute address) register This register indicates the upper 7 bits of the buffer memory address where the minute byte of the current sector (after error correction) is written in bits (Remaining address bits are all low.) MODE1 MODE2, FORM1 MODE2, FORM2 —30— CXD1199AQ ...
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... HXFRC. At any other time, the HXFR (sub CPU register) value is loaded. HXFRC is decremented when data is read from the buffer memory (BFRD is high) or when the IC accepts data from the host (BFWR is high). 2-2-11. HADRC-L (host address counter-low) register —31— CXD1199AQ ...
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... HINTSTS#0 (host interrupt status #0) This is high when the sub CPU writes data into HINT#0 (HIFCTL register bit 0) and low when the host writes “high” into CLRINT#0 (HCLRCTL register bit 0 used to monitor interrupts for the host. —32— CXD1199AQ ...
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... BIT LNGTH “L” Sub CPU write registers —33— CXD1199AQ bit2 bit1 bit0 LSB 1st “L” “L” 9 bit RAM CLK DIS HCLK DIS DAMIX EN DACO DIS “ ...
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... RSL EMPT PRM RRDY DMA BUSY HINT STS2 bit5 bit4 bit3 bit5 bit4 bit3 Sub CPU read registers —34— CXD1199AQ bit2 bit1 bit0 ECC OK C MODE C FORM — SHRT SCT NO SYNC SUB MODE CI CHANNEL bit1 bit0 bit2 ...
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... Setting each bit in this register high enables an interrupt request from the IC to the host depending on the corresponding interrupt status. The value of each bit has no effect on the corresponding interrupt status. bit 7 : Reserved bit 4 : ENBFWRDY (enable buffer write ready interrupt) bit 3 : ENBFEMPT (enable buffer write empty interrupt) bits ENINT (enable interrupt # —35— CXD1199AQ ...
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... Reserved bit 6 : EMPHASIS High : Emphasis ON Low : Emphasis OFF bit 4 : BITLNGTH High : 8 bits Low : 4 bits bit High : 18.9 kHz Low : 37.8 kHz bit 0 : S/M (stereo/mono) High : Stereo Low : Mono 3-1-9. ATV (attenuation value) register 0 3-1-10. ATV (attenuation value) register 1 —36— CXD1199AQ ...
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... Attenuation=20 log ( The relationship expressed in the above formula and ATV register settings is given in the following table. ATV0 DF ATV2 –1 –2 –3 –4 —37— CXD1199AQ L ATV3 ATV1 –5 –6 –7 ...
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... Relationship between ATV register settings and attenuation (dB) —38— Attenuation Setting Attenuation 3.56 2A 9.68 3.66 29 9.89 3.76 28 10.10 3.87 27 10.32 3.97 26 10.55 4.08 25 10.78 4.19 24 11.02 4.30 23 11.26 4.41 22 11.51 4.53 21 11.77 4.64 20 12.04 4.76 1F 12.32 4.88 1E 12.60 5.00 1D 12.90 5.12 1C 13.20 5.24 1B 13.52 5.37 1A 13.84 5.49 19 14.19 5.62 18 14.54 5.75 17 14.91 5.89 16 15.30 6.02 15 15.70 6.16 14 16.12 6.30 13 16.57 6.44 12 17.04 6.58 11 17.54 6.73 10 18.06 6.88 0F 18.62 7.03 0E 19.22 7.18 0D 19.87 7.34 0C 20.56 7.50 0B 21.32 7.66 0A 22.14 7.82 09 23.06 7.99 08 24.08 8.16 07 25.24 8.34 06 26.58 8.52 05 28.16 8.70 04 30.10 8.89 03 32.60 9.08 02 36.12 9.28 01 42.14 9.47 00 CXD1199AQ ...
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... Set high to mute the ADPCM sound for ADPCM decoding. bits Reserved Apart from ATV 2 and 0, all the write registers are initialized to 00HEX when reset (either hard or soft reset). The ATV 2 and 0 registers are initialized to 80HEX when reset. —39— CXD1199AQ ...
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... This register is where the data from the buffer memory is written from the host. Data can be read in the I/O mode or using DMAC. The register has a 2-byte FIFO configuration. 3-2-4. HINTMSK (host interrupt mask) register The values written in the HINTMSK register can be read from this register. —40— CXD1199AQ ...
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... PRM EMPT bit5 bit4 bit3 bit5 bit4 bit3 — ENBF WRDY ENBF EMPT — BF WRDY BF EMPT Host read registers —41— CXD1199AQ bit2 bit1 bit0 “L” RA1 RA0 bit2 bit1 bit0 bit2 bit1 bit0 “L” “L” “L” ...
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... SONY CODE EIAJ CODE JEDEC CODE 100PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0 0.15 0.24 M 0.15 DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-100P-L01 QFP100-P-1420 LEAD MATERIAL PACKAGE MASS —42— CXD1199AQ + 0.1 0.15 – 0. 0.35 2.75 – 0.15 EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g ...