UPD780023AY Renesas Electronics Corporation., UPD780023AY Datasheet
UPD780023AY
Available stocks
Related parts for UPD780023AY
UPD780023AY Summary of contents
Page 1
User’s Manual µ PD780024A, 780034A, 780024AY, 780034AY Subseries 8-Bit Single-Chip Microcontrollers µ PD780021A µ PD780022A µ PD780023A µ PD780024A µ PD780021A(A) µ PD780022A(A) µ PD780023A(A) µ PD780024A(A) Document No. U14046EJ5V0UD00 (5th edition) Date Published March 2005 N CP(K) © 1999, ...
Page 2
User’s Manual U14046EJ5V0UD ...
Page 3
NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
Page 4
EEPROM, FIP, and IEBus are trademarks of NEC Electronics Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. HP9000 ...
Page 5
These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of February, ...
Page 6
Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and ...
Page 7
Readers This manual has been prepared for user engineers who understand the functions of the µ PD780024A, 780034A, 780024AY, and 780034AY Subseries and wish to design and develop application systems and programs for these devices. • µ PD780024A Subseries µ ...
Page 8
How To Read This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. • For readers who use this as an (A) product: → Standard products ...
Page 9
Chapter Organization This manual divides the descriptions for the subseries into different chapters as shown below. Read only the chapters related to the device you use. Chapter Outline ( µ PD780024A, 780034A Subseries) Chapter 1 Outline ( µ PD780024AY, 780034AY ...
Page 10
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices µ PD780024A, 780034A, 780024AY, 780034AY Subseries User’s Manual 78K/0 Series Instructions User’s Manual 78K/0 Series ...
Page 11
Other Documents SEMICONDUCTOR SELECTION GUIDE − Products and Packages − Semiconductor Device Mount Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the ...
Page 12
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) .................................................... 1.1 Expanded-Specification Products and Conventional Products ....................................... 1.2 Features ................................................................................................................................. 1.3 Applications .......................................................................................................................... 1.4 Ordering Information ............................................................................................................ 1.5 Quality Grade ........................................................................................................................ 1.6 Pin Configuration (Top View) ............................................................................................... 1.7 78K/0 Series Lineup ...
Page 13
X1 and X2 .................................................................................................................................. 3.2.15 XT1 and XT2 .............................................................................................................................. 3.2.16 V and V ............................................................................................................................. DD0 DD1 3.2.17 V and V ............................................................................................................................. SS0 SS1 3.2.18 V (flash memory versions only) .............................................................................................. PP 3.2.19 IC (mask ROM version only) ...................................................................................................... 3.3 ...
Page 14
Operand Address Addressing ............................................................................................. 125 5.4.1 Implied addressing ..................................................................................................................... 125 5.4.2 Register addressing ................................................................................................................... 126 5.4.3 Direct addressing ....................................................................................................................... 127 5.4.4 Short direct addressing .............................................................................................................. 128 5.4.5 Special function register (SFR) addressing ................................................................................ 129 5.4.6 Register indirect addressing ....................................................................................................... ...
Page 15
Registers to Control 16-Bit Timer/Event Counter 0 ........................................................... 186 8.4 Operation of 16-Bit Timer/Event Counter 0 ........................................................................ 192 8.4.1 Interval timer operation .............................................................................................................. 192 8.4.2 External event counter operation ............................................................................................... 195 8.4.3 Pulse width measurement operations ........................................................................................ 197 8.4.4 ...
Page 16
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER ............................................ 250 12.1 Clock Output/Buzzer Output Controller Functions ........................................................... 250 12.2 Configuration of Clock Output/Buzzer Output Controller ................................................. 251 12.3 Register to Control Clock Output/Buzzer Output Controller ............................................ 251 12.4 Operation of Clock Output/Buzzer ...
Page 17
CHAPTER 18 SERIAL INTERFACE IIC0 ( µ PD780024AY, 780034AY SUBSERIES ONLY) ..... 338 18.1 Functions of Serial Interface IIC0 ........................................................................................ 338 18.2 Configuration of Serial Interface IIC0 .................................................................................. 341 18.3 Registers to Control Serial Interface IIC0 ........................................................................... 343 2 18.4 ...
Page 18
CHAPTER 22 RESET FUNCTION .................................................................................................... 439 CHAPTER 23 µ PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY .............................................. 443 23.1 Differences Between µ PD78F0034A, 78F0034AY and µ PD78F0034B, 78F0034BY ......... 444 23.2 Differences Between µ PD78F0034B, 78F0034BY and µ PD78F0034B(A), 78F0034BY(A) ........................................................................................................................ 445 23.3 ...
Page 19
APPENDIX C NOTES ON TARGET SYSTEM DESIGN ................................................................ 581 APPENDIX D REGISTER INDEX ...................................................................................................... 591 D.1 Register Name Index ............................................................................................................ 591 D.2 Register Symbol Index ......................................................................................................... 594 APPENDIX E REVISION HISTORY .................................................................................................. 597 E.1 Major Revisions in This Edition ........................................................................................... ...
Page 20
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.1 Expanded-Specification Products and Conventional Products The expanded-specification products and conventional products refer to the following products. Expanded-specification products: µ PD780021A, 780022A, 780023A, 780024A, 780031A, 780032A, 780033A, Conventional products: Note The rank ...
Page 21
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.2 Features • Internal memory Type Program Memory Part Number (ROM/Flash Memory) µ PD780021A, 780031A 8 KB µ PD780022A, 780032A 16 KB µ PD780023A, 780033A 24 KB µ PD780024A, 780034A 32 KB ...
Page 22
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.3 Applications µ PD780021A, 780022A, 780023A, 780024A µ PD780031A, 780032A, 780033A, 780034A, 78F0034A, 78F0034B Home electric appliances, pagers, AV equipment, car audios, office automation equipment, etc. µ PD780021A(A), 780022A(A), 780023A(A), 780024A(A) µ ...
Page 23
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.4 Ordering Information (1) µ PD780024A Subseries (1/3) Part Number µ PD780021ACW-××× µ PD780021ACW-×××-A Note 1 µ PD780021AGC-×××-AB8 µ PD780021AGC-×××-AB8-A Note 1 µ PD780021AGC-×××-8BS µ PD780021AGC-×××-8BS-A µ PD780021AGK-×××-9ET µ PD780021AGK-×××-9ET-A µ PD780021AGB-×××-8EU ...
Page 24
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (1) µ PD780024A Subseries (2/3) Part Number µ PD780023ACW-××× µ PD780023ACW-×××-A Note 1 µ PD780023AGC-×××-AB8 µ PD780023AGC-×××-AB8-A Note 1 µ PD780023AGC-×××-8BS µ PD780023AGC-×××-8BS-A µ PD780023AGK-×××-9ET µ PD780023AGK-×××-9ET-A µ PD780023AGB-×××-8EU µ PD780023AGB-×××-8EU-A µ ...
Page 25
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (1) µ PD780024A Subseries (3/3) Part Number µ PD780021ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) µ PD780021AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) µ PD780021AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) µ ...
Page 26
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (2) µ PD780034A Subseries (1/4) Part Number µ ××× PD780031ACW- 64-pin plastic SDIP (19.05 mm (750)) µ ××× Note 1 PD780031ACW- -A 64-pin plastic SDIP (19.05 mm (750)) µ ××× PD780031AGC- -AB8 ...
Page 27
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (2) µ PD780034A Subseries (2/4) Part Number µ PD780033ACW-××× 64-pin plastic SDIP (19.05 mm (750)) µ PD780033ACW-×××-A Note 1 64-pin plastic SDIP (19.05 mm (750)) µ PD780033AGC-×××-AB8 64-pin plastic QFP (14 × ...
Page 28
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (2) µ PD780034A Subseries (3/4) Part Number µ PD78F0034ACW 64-pin plastic SDIP (19.05 mm (750)) µ PD78F0034ACW-A Note 1 64-pin plastic SDIP (19.05 mm (750)) µ PD78F0034AGC-AB8 64-pin plastic QFP (14 × ...
Page 29
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (2) µ PD780034A Subseries (4/4) Part Number µ PD780031ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) µ PD780031AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) µ PD780031AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) µ ...
Page 30
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.5 Quality Grade (1) µ PD780024A Subseries (1/3) Part Number µ PD780021ACW-××× 64-pin plastic SDIP (19.05 mm (750)) µ PD780021ACW-×××-A Note 1 64-pin plastic SDIP (19.05 mm (750)) µ PD780021AGC-×××-AB8 64-pin plastic ...
Page 31
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (1) µ PD780024A Subseries (2/3) Part Number µ PD780023ACW-××× 64-pin plastic SDIP (19.05 mm (750)) µ PD780023ACW-×××-A Note 1 64-pin plastic SDIP (19.05 mm (750)) µ PD780023AGC-×××-AB8 64-pin plastic QFP (14 × ...
Page 32
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (1) µ PD780024A Subseries (3/3) Part Number µ PD780021ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) µ PD780021AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) µ PD780021AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) µ ...
Page 33
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (2) µ PD780034A Subseries (1/4) Part Number µ PD780031ACW-××× 64-pin plastic SDIP (19.05 mm (750)) µ PD780031ACW-×××-A Note 1 64-pin plastic SDIP (19.05 mm (750)) µ PD780031AGC-×××-AB8 64-pin plastic QFP (14 × ...
Page 34
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (2) µ PD780034A Subseries (2/4) Part Number µ PD780033ACW-××× 64-pin plastic SDIP (19.05 mm (750)) µ PD780033ACW-×××-A Note 1 64-pin plastic SDIP (19.05 mm (750)) µ PD780033AGC-×××-AB8 64-pin plastic QFP (14 × ...
Page 35
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (2) µ PD780034A Subseries (3/4) Part Number µ PD78F0034ACW 64-pin plastic SDIP (19.05 mm (750)) µ PD78F0034ACW-A Note 1 64-pin plastic SDIP (19.05 mm (750)) µ PD78F0034AGC-AB8 64-pin plastic QFP (14 × ...
Page 36
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) (2) µ PD780034A Subseries (4/4) Part Number µ PD780031ACW(A)-××× 64-pin plastic SDIP (19.05 mm (750)) µ PD780031AGC(A)-×××-AB8 64-pin plastic QFP (14 × 14) µ PD780031AGC(A)-×××-8BS 64-pin plastic LQFP (14 × 14) µ ...
Page 37
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.6 Pin Configuration (Top View) • 64-pin plastic SDIP (19.05 mm (750)) P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 V SS0 V DD0 ...
Page 38
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) • 64-pin plastic QFP (14 × 14) • 64-pin plastic LQFP (14 × 14) • 64-pin plastic TQFP (12 × 12) • 64-pin plastic LQFP (10 × 10 ...
Page 39
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) • 73-pin plastic FBGA (9 × 9) Top View Index mark Pin No. Pin Name Pin No. Pin Name P52/A10 ...
Page 40
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES A15: Address bus AD0 to AD7: Address/data bus ADTRG: AD trigger input ANI0 to ANI7: Analog input ASCK0: Asynchronous serial clock ASTB: Address strobe AV : Analog power supply DD ...
Page 41
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.7 78K/0 Series Lineup The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name. Products in mass production Control µ PD78075B 100-pin µ PD78078 100-pin ...
Page 42
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) The major functional differences between the subseries are shown below. • Subseries without the suffix Y Function ROM Capacity 8-Bit 16-Bit Watch WDT A/D Subseries Name µ PD78075B ...
Page 43
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.8 Block Diagram TI00/TO0/P70 16-bit timer/ event counter 0 TI01/P71 8-bit timer/ TI50/TO50/P72 event counter 50 8-bit timer/ TI51/TO51/P73 event counter 51 Watchdog timer Watch timer SI30/P20 Serial SO30/P21 interface SIO30 SCK30/P22 ...
Page 44
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.9 Outline of Function Part Number Item Internal memory ROM High-speed RAM Memory space General-purpose register Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction set I/O ...
Page 45
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) Part Number Item Power supply voltage Operating ambient temperature Package The outline of the timer/event counter is as follows (for details, see CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0, CHAPTER 9 8-BIT TIMER/EVENT ...
Page 46
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.10 Correspondence Between Mask ROM Versions and Flash Memory Versions Table 1-1. Correspondence Between Mask ROM Versions and Flash Memory Versions Mask ROM Version Flash Memory Version µ PD78F0034A µ PD78F0034B µ ...
Page 47
CHAPTER 1 OUTLINE ( µ PD780024A, 780034A SUBSERIES) 1.12 Correspondence Between Products and Packages The following table shows the correspondence between the products and packages. Table 1-3. Correspondence Between Products and Packages Mask ROM Version µ PD780021A/2A/3A/4A µ PD780031A/2A/3A/4A Standard ...
Page 48
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.1 Features • Internal memory Type Part Number (ROM/Flash Memory) µ PD780021AY, 780031AY 8 KB µ PD780022AY, 780032AY 16 KB µ PD780023AY, 780033AY 24 KB µ PD780024AY, 780034AY 32 KB µ PD78F0034AY, ...
Page 49
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.2 Applications µ PD780021AY, 780022AY, 780023AY, 780024AY µ PD780031AY, 780032AY, 780033AY, 780034AY, 78F0034AY, 78F0034BY Home electric appliances, pagers, AV equipment, car audios, office automation equipment, etc. µ PD780021AY(A), 780022AY(A), 780023AY(A), 780024AY(A) µ ...
Page 50
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.3 Ordering Information (1) µ PD780024AY Subseries (1/3) Part Number µ PD780021AYCW-××× µ PD780021AYCW-×××-A Note 1 µ PD780021AYGC-×××-AB8 µ PD780021AYGC-×××-AB8-A Note 1 µ PD780021AYGC-×××-8BS µ PD780021AYGC-×××-8BS-A Note 2 µ PD780021AYGK-×××-9ET µ PD780021AYGK-×××-9ET-A ...
Page 51
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (1) µ PD780024AY Subseries (2/3) Part Number µ PD780023AYCW-××× µ PD780023AYCW-×××-A Note 1 µ PD780023AYGC-×××-AB8 µ PD780023AYGC-×××-AB8-A Note 1 µ PD780023AYGC-×××-8BS µ PD780023AYGC-×××-8BS-A Note 2 µ PD780023AYGK-×××-9ET µ PD780023AYGK-×××-9ET-A µ PD780023AYGB-×××-8EU µ ...
Page 52
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (1) µ PD780024AY Subseries (3/3) Part Number µ PD780021AYCW(A)-××× Note 64-pin plastic SDIP (19.05 mm (750)) µ PD780021AYGC(A)-×××-AB8 Note 64-pin plastic QFP (14 × 14) µ PD780021AYGC(A)-×××-8BS 64-pin plastic LQFP (14 × ...
Page 53
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (2) µ PD780034AY Subseries (1/4) Part Number µ PD780031AYCW-××× µ PD780031AYCW-×××-A Note 1 µ PD780031AYGC-×××-AB8 µ PD780031AYGC-×××-AB8-A Note 1 µ PD780031AYGC-×××-8BS µ PD780031AYGC-×××-8BS-A µ PD780031AYGK-×××-9ET µ PD780031AYGK-×××-9ET-A Note 2 µ PD780031AYGB-×××-8EU µ ...
Page 54
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (2) µ PD780034AY Subseries (2/4) Part Number µ PD780033AYCW-××× µ PD780033AYCW-×××-A Note 1 µ PD780033AYGC-×××-AB8 µ PD780033AYGC-×××-AB8-A Note 1 µ PD780033AYGC-×××-8BS µ PD780033AYGC-×××-8BS-A µ PD780033AYGK-×××-9ET µ PD780033AYGK-×××-9ET-A Note 2 µ PD780033AYGB-×××-8EU µ ...
Page 55
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (2) µ PD780034AY Subseries (3/4) Part Number µ PD78F0034AYCW µ PD78F0034AYCW-A Note 2 µ PD78F0034AYGC-AB8 µ PD78F0034AYGC-AB8-A Note 1 µ PD78F0034AYGC-8BS µ PD78F0034AYGC-8BS-A Note 2 µ PD78F0034AYGK-9ET µ PD78F0034AYGK-9ET-A Note 1 µ ...
Page 56
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (2) µ PD780034AY Subseries (4/4) Part Number µ PD780031AYCW(A)-××× Note 64-pin plastic SDIP (19.05 mm (750)) µ PD780031AYGC(A)-×××-AB8 Note 64-pin plastic QFP (14 × 14) µ PD780031AYGC(A)-×××-8BS 64-pin plastic LQFP (14 × ...
Page 57
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.4 Quality Grade (1) µ PD780024AY Subseries (1/3) Part Number µ PD780021AYCW-××× µ PD780021AYCW-×××-A Note 1 µ PD780021AYGC-×××-AB8 µ PD780021AYGC-×××-AB8-A Note 1 µ PD780021AYGC-×××-8BS µ PD780021AYGC-×××-8BS-A Note 2 µ PD780021AYGK-×××-9ET µ PD780021AYGK-×××-9ET-A ...
Page 58
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (1) µ PD780024AY Subseries (2/3) Part Number µ PD780023AYCW-××× µ PD780023AYCW-×××-A Note 1 µ PD780023AYGC-×××-AB8 µ PD780023AYGC-×××-AB8-A Note 1 µ PD780023AYGC-×××-8BS µ PD780023AYGC-×××-8BS-A Note 2 µ PD780023AYGK-×××-9ET µ PD780023AYGK-×××-9ET-A µ PD780023AYGB-×××-8EU µ ...
Page 59
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (1) µ PD780024AY Subseries (3/3) Part Number µ PD780021AYCW(A)-××× Note 64-pin plastic SDIP (19.05 mm (750)) µ PD780021AYGC(A)-×××-AB8 Note 64-pin plastic QFP (14 × 14) µ PD780021AYGC(A)-×××-8BS 64-pin plastic LQFP (14 × ...
Page 60
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (2) µ PD780034AY Subseries (1/4) Part Number µ PD780031AYCW-××× µ PD780031AYCW-×××-A Note 1 µ PD780031AYGC-×××-AB8 µ PD780031AYGC-×××-AB8-A Note 1 µ PD780031AYGC-×××-8BS µ PD780031AYGC-×××-8BS-A µ PD780031AYGK-×××-9ET µ PD780031AYGK-×××-9ET-A Note 2 µ PD780031AYGB-×××-8EU µ ...
Page 61
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (2) µ PD780034AY Subseries (2/4) Part Number µ PD780033AYCW-××× µ PD780033AYCW-×××-A Note 1 µ PD780033AYGC-×××-AB8 µ PD780033AYGC-×××-AB8-A Note 1 µ PD780033AYGC-×××-8BS µ PD780033AYGC-×××-8BS-A µ PD780033AYGK-×××-9ET µ PD780033AYGK-×××-9ET-A Note 2 µ PD780033AYGB-×××-8EU µ ...
Page 62
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (2) µ PD780034AY Subseries (3/4) Part Number µ PD78F0034AYCW µ PD78F0034AYCW-A Note 2 µ PD78F0034AYGC-AB8 µ PD78F0034AYGC-AB8-A Note 1 µ PD78F0034AYGC-8BS µ PD78F0034AYGC-8BS-A Note 2 µ PD78F0034AYGK-9ET µ PD78F0034AYGK-9ET-A Note 1 µ ...
Page 63
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) (2) µ PD780034AY Subseries (4/4) Part Number µ PD780031AYCW(A)-××× Note 64-pin plastic SDIP (19.05 mm (750)) µ PD780031AYGC(A)-×××-AB8 Note 64-pin plastic QFP (14 × 14) µ PD780031AYGC(A)-×××-8BS 64-pin plastic LQFP (14 × ...
Page 64
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.5 Pin Configuration (Top View) • 64-pin plastic SDIP (19.05 mm (750)) P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 P56/A14 P57/A15 V SS0 V DD0 ...
Page 65
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) • 64-pin plastic QFP (14 × 14) • 64-pin plastic LQFP (14 × 14) • 64-pin plastic TQFP (12 × 12) • 64-pin plastic LQFP (10 × 10 ...
Page 66
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) • 73-pin plastic FBGA (9 × 9) Top View Index mark Pin No. Pin Name Pin No. Pin Name P52/A10 ...
Page 67
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES A15: Address bus AD0 to AD7: Address/data bus ADTRG: AD trigger input ANI0 to ANI7: Analog input ASCK0: Asynchronous serial clock ASTB: Address strobe AV : Analog power supply DD ...
Page 68
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.6 78K/0 Series Lineup The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries name. Products in mass production Control µ PD78075B 100-pin µ PD78078 100-pin ...
Page 69
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) The major functional differences between the subseries are shown below. • Subseries with the suffix Y Function ROM Capacity 8-Bit 16-Bit Watch WDT A/D Subseries Name µ PD78078Y Control ...
Page 70
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.7 Block Diagram TI00/TO0/P70 16-bit timer/ event counter 0 TI01/P71 8-bit timer/ TI50/TO50/P72 event counter 50 8-bit timer/ TI51/TO51/P73 event counter 51 Watchdog timer Watch timer SI30/P20 Serial SO30/P21 interface SIO30 SCK30/P22 ...
Page 71
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.8 Outline of Function Part Number Item Internal memory ROM High-speed RAM Memory space General-purpose register Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction set I/O ...
Page 72
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) The outline of the timer/event counter is as follows (for details, see CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0, CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 50, 51, CHAPTER 10 WATCH TIMER, and CHAPTER 11 ...
Page 73
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.10 Differences Between Standard Grade Products and Special Grade Products The differences between standard grade products ( µ PD780021AY, 780022AY, 780023AY, 780024AY, 780031AY, 780032AY, 780033AY, 780034AY, 78F0034AY, 78F0034BY) and special grade products ...
Page 74
CHAPTER 2 OUTLINE ( µ PD780024AY, 780034AY SUBSERIES) 2.12 Mask Options The mask ROM versions ( µ PD780021AY, 780022AY, 780023AY, 780024AY, 780031AY, 780032AY, 780033AY, 780034AY) provide pull-up resistor mask options which allow users to specify whether to connect a pull-up ...
Page 75
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) 3.1 Pin Function List (1) Port pins (1/2) Pin Name I/O P00 I/O Port 0 4-bit I/O port P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up ...
Page 76
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) (1) Port pins (2/2) Pin Name I/O P70 I/O Port 7 6-bit I/O port P71 Input/output mode can be specified in 1-bit units. P72 An on-chip pull-up resistor can be used ...
Page 77
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) (2) Non-port pins (2/2) Pin Name I A15 Output Higher address bus when expanding external memory RD Output Strobe signal output for read operation from external memory WR Strobe ...
Page 78
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) 3.2 Description of Pin Functions 3.2.1 P00 to P03 (Port 0) These are 4-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt input, and A/D converter ...
Page 79
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) 3.2.3 P20 to P25 (Port 2) These are 6-bit I/O ports. Besides serving as I/O ports, they function as data I/O and clock I/O of serial interface SIO30 or UART0. The ...
Page 80
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) 3.2.5 P40 to P47 (Port 4) These are 8-bit I/O ports. Besides serving as I/O ports, they function as an address/data bus. The interrupt request flag (KRIF) can be set to ...
Page 81
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) 3.2.8 P70 to P75 (Port 7) These are 6-bit I/O ports. Besides serving as I/O ports, they function as a timer I/O, clock output, and buzzer output. The following operating modes ...
Page 82
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) 3.2.12 RESET This is a low-level active system reset input pin. 3.2. (Non-connection) pin is not internally connected. Leave this pin open. 3.2.14 X1 and X2 Crystal/ceramic resonator connection ...
Page 83
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 3-1 shows the types of pin I/O circuit and the recommended connections of unused pins. See Figure 3-1 for the ...
Page 84
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) Pin Name I/O Circuit Type P50/A8 to P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL P75/BUZ RESET Note NC XT1 XT2 REF (for ...
Page 85
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) Figure 3-1. Pin I/O Circuit List (1/2) Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-H Pullup enable V DD0 Data P-ch Output N-ch disable V SS0 Input enable Type ...
Page 86
CHAPTER 3 PIN FUNCTION ( µ PD780024A, 780034A SUBSERIES) Type 13-S Mask option Data Output disable V Type 16 Feedback cut-off P-ch XT1 XT2 86 Figure 3-1. Pin I/O Circuit List (2/2) Type 25 V DD0 ...
Page 87
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) 4.1 Pin Function List (1) Port pins (1/2) Pin Name I/O P00 I/O Port 0 4-bit I/O port P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up ...
Page 88
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) (1) Port pins (2/2) Pin Name I/O P70 I/O Port 7 6-bit I/O port P71 Input/output mode can be specified in 1-bit units. P72 An on-chip pull-up resistor can be used ...
Page 89
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) (2) Non-port pins (2/2) Pin Name I/O WAIT Input Wait insertion when accessing external memory ASTB Output Strobe output externally latching address information output to ports access external ...
Page 90
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) 4.2 Description of Pin Functions 4.2.1 P00 to P03 (Port 0) These are 4-bit I/O ports. Besides serving as I/O ports, they function as an external interrupt input, and A/D converter ...
Page 91
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) 4.2.3 P20 to P25 (Port 2) These are 6-bit I/O ports. Besides serving as I/O ports, they function as serial interface data I/O and clock I/O. The following operating modes can ...
Page 92
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) 4.2.5 P40 to P47 (Port 4) These are 8-bit I/O ports. Besides serving as I/O ports, they function as an address/data bus. The interrupt request flag (KRIF) can be set to ...
Page 93
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) 4.2.8 P70 to P75 (Port 7) These are 6-bit I/O ports. Besides serving as I/O ports, they function as a timer I/O, clock output, and buzzer output. The following operating modes ...
Page 94
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) 4.2.12 RESET This is a low-level active system reset input pin. 4.2. (Non-connection) pin is not internally connected. Leave this pin open. 4.2.14 X1 and X2 Crystal/ceramic resonator connection ...
Page 95
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) 4.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 4-1 shows the types of pin I/O circuit and the recommended connections of unused pins. See Figure 4-1 for the ...
Page 96
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) Pin Name I/O Circuit Type P50/A8 to P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/TI00/TO0 P71/TI01 P72/TI50/TO50 P73/TI51/TO51 P74/PCL P75/BUZ RESET Note NC XT1 XT2 REF (for ...
Page 97
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) Figure 4-1. Pin I/O Circuit List (1/2) Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-H Pullup enable V DD0 Data P-ch Output N-ch disable V SS0 Input enable Type ...
Page 98
CHAPTER 4 PIN FUNCTION ( µ PD780024AY, 780034AY SUBSERIES) Type 16 Feedback cut-off P-ch XT1 XT2 98 Figure 4-1. Pin I/O Circuit List (2/2) Type 25 Comparator Input enable User’s Manual U14046EJ5V0UD P-ch + — N-ch V SS0 IN V ...
Page 99
CHAPTER 5 CPU ARCHITECTURE 5.1 Memory Spaces PD780024A, 780034A, 780024AY, 780034AY Subseries can access 64 KB memory space respectively. Figures 5-1 to 5-5 show memory maps. Caution In case of the internal memory capacity, the initial value of memory size ...
Page 100
Figure 5-2. Memory Map ( PD780022A, 780032A, 780022AY, 780032AY) FFFFH FF00H General-purpose FEFFH FEE0H FEDFH Internal high-speed RAM FD00H FCFFH Data memory space F800H F7FFH Program memory space 4000H 3FFFH 0000H 100 CHAPTER 5 CPU ARCHITECTURE Special function registers (SFRs) ...
Page 101
CHAPTER 5 CPU ARCHITECTURE Figure 5-3. Memory Map ( PD780023A, 780033A, 780023AY, 780033AY) FFFFH Special function registers (SFRs) FF00H General-purpose FEFFH registers FEE0H 32 FEDFH Internal high-speed RAM FB00H FAFFH Data memory space F800H F7FFH External memory 38912 Program memory ...
Page 102
Figure 5-4. Memory Map ( PD780024A, 780034A, 780024AY, 780034AY) FFFFH FF00H General-purpose FEFFH FEE0H FEDFH Internal high-speed RAM FB00H FAFFH Data memory space F800H F7FFH Program memory space 8000H 7FFFH 0000H 102 CHAPTER 5 CPU ARCHITECTURE Special function registers (SFRs) ...
Page 103
Figure 5-5. Memory Map ( PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY) FFFFH Special function registers (SFRs) FF00H General-purpose FEFFH registers FEE0H 32 FEDFH Internal high-speed RAM FB00H FAFFH Data memory space F800H F7FFH External memory Program memory space 8000H 7FFFH Flash memory ...
Page 104
Internal program memory space The internal program memory space contains the program and table data. Normally addressed with the program counter (PC). The PD780024A, 780034A, 780024AY, and 780034AY Subseries products incorporate an on-chip ROM (mask ROM or ...
Page 105
Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of ...
Page 106
Internal data memory space The PD780024A, 780034A, 780024AY, and 780034AY Subseries products incorporate an internal high-speed RAM, as listed below. Table 5-3. Internal High-Speed RAM Capacity Part Number PD780021A, 780031A, 780021AY, 780031AY PD780022A, 780032A, 780022AY, 780032AY PD780023A, 780033A, 780023AY, ...
Page 107
Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for ...
Page 108
Figure 5-7. Correspondence Between Data Memory and Addressing ( PD780022A, 780032A, 780022AY, 780032AY) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 512 8 bits FE20H FE1FH ...
Page 109
CHAPTER 5 CPU ARCHITECTURE Figure 5-8. Correspondence Between Data Memory and Addressing ( PD780023A, 780033A, 780023AY, 780033AY) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 ...
Page 110
Figure 5-9. Correspondence Between Data Memory and Addressing ( PD780024A, 780034A, 780024AY, 780034AY) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 8 bits FE20H FE1FH ...
Page 111
CHAPTER 5 CPU ARCHITECTURE Figure 5-10. Correspondence Between Data Memory and Addressing ( PD78F0034A, 78F0034B, 78F0034AY, 78F0034BY) FFFFH Special function registers (SFRs) 256 8 bits FF20H FF1FH FF00H FEFFH General-purpose registers 32 8 bits FEE0H FEDFH Internal high-speed RAM 1024 ...
Page 112
Processor Registers The PD780024A, 780034A, 780024AY, 780034AY Subseries products incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program ...
Page 113
Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE is set to the disable interrupt (DI) state, and only non-maskable interrupt request becomes acknowledgeable. Other interrupt requests are all ...
Page 114
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. ...
Page 115
CHAPTER 5 CPU ARCHITECTURE Figure 5-15. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP is FEDEH) SP FEE0H FEE0H FEDFH SP FEDEH FEDEH (b) RET instruction (when SP is FEDEH) SP FEE0H FEE0H FEDFH SP ...
Page 116
General-purpose registers A general-purpose register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). Each ...
Page 117
Special function register (SFR) Unlike a general-purpose register, each special function register has special functions allocated in the FF00H to FFFFH area. The special function register can be manipulated like the general-purpose register, with the operation, transfer ...
Page 118
Table 5-5. Special Function Register List (1/3) Address Special Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF02H Port 2 FF03H Port 3 FF04H Port 4 FF05H Port 5 FF06H Port 6 FF07H Port 7 FF0AH 16-bit timer ...
Page 119
Table 5-5. Special Function Register List (2/3) Address Special Function Register (SFR) Name FF20H Port mode register 0 FF22H Port mode register 2 FF23H Port mode register 3 FF24H Port mode register 4 FF25H Port mode register 5 FF26H Port ...
Page 120
Table 5-5. Special Function Register List (3/3) Address Special Function Register (SFR) Name Note 1 FFA8H IIC control register 0 Note 1 FFA9H IIC status register 0 FFAAH IIC transfer clock select register 0 Note 1 FFABH Slave address register ...
Page 121
Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is ...
Page 122
Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
Page 123
Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
Page 124
Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration ...
Page 125
Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 5.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general-purpose ...
Page 126
Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register specify code (Rn and RPn instruction word in the registered bank specified with the register bank select flag (RBS0 and ...
Page 127
Direct addressing [Function] The memory to be manipulated is addressed with immediate data in an instruction word becoming an operand address. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] 7 addr16 (lower) ...
Page 128
Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function ...
Page 129
Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
Page 130
Register indirect addressing [Function] Register pair contents specified with a register pair specify code in an instruction word of the register bank specified with a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing ...
Page 131
Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in an instruction word of the register bank specified by the register bank select flags ...
Page 132
Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank ...
Page 133
Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
Page 134
CHAPTER 6 PORT FUNCTIONS 6.1 Port Functions The µ PD780024A, 780034A, 780024AY, and 780034AY Subseries products incorporate eight input ports and 43 I/O ports. Figure 6-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and ...
Page 135
Table 6-1. Port Functions ( µ PD780024A, 780034A Subseries) Pin Name P00 Port 0 4-bit I/O port. P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up resistor can be used by software settings. P03 P10 to ...
Page 136
Table 6-2. Port Functions ( µ PD780024AY, 780034AY Subseries) Pin Name P00 Port 0 4-bit I/O port. P01 Input/output mode can be specified in 1-bit units. P02 An on-chip pull-up resistor can be used by software settings. P03 P10 to ...
Page 137
Port Configuration A port consists of the following hardware. Item Control register Port Pull-up resistor Note Two mask options for the µ PD780024AY and 780034AY Subseries. 6.2.1 Port 0 Port 4-bit I/O port with output latch. ...
Page 138
Figure 6-2. Block Diagram of P00 to P03 WR PU PU00 to PU03 Alternate function RD WR PORT Output latch (P00 to P03 PM00 to PM03 PU: Pull-up resistor option register PM: Port mode register RD: Port 0 ...
Page 139
Port 1 Port 8-bit input-only port. This port can also be used as an A/D converter analog input. Figure 6-3 shows a block diagram of port 1. Figure 6-3. Block Diagram of P10 to P17 RD ...
Page 140
Port 2 Port 6-bit I/O port with output latch. P20 to P25 pins can specify the input mode/output mode in 1-bit units with port mode register 2 (PM2). An on-chip pull-up resistor of P20 to P25 ...
Page 141
CHAPTER 6 PORT FUNCTIONS Figure 6-5. Block Diagram of P21 and P24 WR PU PU21, PU24 RD WR PORT Output latch (P21, P24 PM21, PM24 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port ...
Page 142
WR PU PU22 Alternate function RD WR PORT Output latch (P22 PM22 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal 142 CHAPTER 6 PORT FUNCTIONS ...
Page 143
Port 3 ( µ PD780024A, 780034A Subseries) Port 7-bit I/O port with output latch. P30 to P36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (PM3). This port has ...
Page 144
Figure 6-8. Block Diagram of P32 and P33 ( µ PD780024A, 780034A Subseries PORT Output latch (P32, P33 PM32, PM33 PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal 144 CHAPTER ...
Page 145
CHAPTER 6 PORT FUNCTIONS Figure 6-9. Block Diagram of P34 ( µ PD780024A, 780034A Subseries PU34 Alternate function RD WR PORT Output latch (P34 PM34 PU: Pull-up resistor option register PM: Port mode register RD: Port ...
Page 146
Figure 6-10. Block Diagram of P35 ( µ PD780024A, 780034A Subseries PU35 RD WR PORT Output latch (P35 PM35 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal WR: ...
Page 147
CHAPTER 6 PORT FUNCTIONS Figure 6-11. Block Diagram of P36 ( µ PD780024A, 780034A Subseries PU36 Alternate function RD WR PORT Output latch (P36 PM36 Alternate function PU: Pull-up resistor option register PM: Port mode register ...
Page 148
Port 3 ( µ PD780024AY, 780034AY Subseries) Port 7-bit I/O port with output latch. P30 to P36 pins can specify the input mode/output mode in 1-bit units with port mode register 3 (PM3). This port has ...
Page 149
CHAPTER 6 PORT FUNCTIONS Figure 6-12. Block Diagram of P30 and P31 ( µ PD780024AY, 780034AY Subseries PORT Output latch (P30, P31 PM30, PM31 PM: Port mode register RD: Port 3 read signal WR: Port 3 ...
Page 150
Figure 6-14. Block Diagram of P34 and P36 ( µ PD780024AY, 780034AY Subseries PU34, PU36 RD WR PORT Output latch (P34, P36 PM34, PM36 PU: Pull-up resistor option register PM: Port mode register RD: Port 3 ...
Page 151
CHAPTER 6 PORT FUNCTIONS Figure 6-15. Block Diagram of P35 ( µ PD780024AY, 780034AY Subseries PU35 RD WR PORT Output latch (P35 PM35 PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read ...
Page 152
Port 4 Port 8-bit I/O port with output latch. The P40 to P47 pins can specify the input mode/output mode in 1- bit units with port mode register 4 (PM4). An on-chip pull-up resistor of P40 ...
Page 153
Figure 6-17. Block Diagram of Falling Edge Detector P40 P41 P42 P43 P44 P45 P46 P47 6.2.7 Port 5 Port 8-bit I/O port with output latch. The P50 to P57 pins can specify the input mode/output mode ...
Page 154
Port 6 Port 4-bit I/O port with output latch. The P64 to P67 pins can specify the input mode/output mode in 1-bit units with port mode register 6 (PM6). An on-chip pull-up resistor of P64 to ...
Page 155
CHAPTER 6 PORT FUNCTIONS Figure 6-20. Block Diagram of P66 WR PU PU66 RD WR PORT Output latch (P66 PM66 PU: Pull-up resistor option register PM: Port mode register RD: Port 6 read signal WR: Port 6 write ...
Page 156
Port 7 Port 6-bit I/O port with output latch. The P70 to P75 pins can specify the input mode/output mode in 1-bit units with port mode register 7 (PM7). An on-chip pull-up resistor of P70 to ...
Page 157
CHAPTER 6 PORT FUNCTIONS Figure 6-22. Block Diagram of P71 WR PU PU71 Alternate function RD WR PORT Output latch (P71 PM71 PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: Port ...
Page 158
Figure 6-23. Block Diagram of P74 and P75 WR PU PU74, PU75 RD WR PORT Output latch (P74, P75 PM74, PM75 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: ...
Page 159
Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM2 to PM7) • Pull-up resistor option registers (PU0, PU2 to PU7) (1) Port mode registers (PM0, PM2 to PM7) These ...
Page 160
Figure 6-24. Format of Port Mode Register (PM0, PM2 to PM7) Address: FF20H After Reset: FFH Symbol 7 6 PM0 1 1 Address: FF22H After Reset: FFH Symbol 7 6 PM2 1 1 Address: FF23H After Reset: FFH Symbol 7 ...
Page 161
Table 6-6. Port Mode Registers and Output Latch Settings When Alternate Function Is Used (1/2) Pin Name P00 to P02 INTP0 to INTP2 P03 INTP3 ADTRG P10 to P17 ANI0 to ANI7 P20 SI30 P21 SO30 P22 SCK30 P23 RxD0 ...
Page 162
Table 6-6. Port Mode Registers and Output Latch Settings When Alternate Function Is Used (2/2) Pin Name P70 TI00 TO0 P71 TI01 P72 TI50 TO50 P73 TI51 TO51 P74 PCL P75 BUZ Remark ×: Don’t care PM××: Port mode register ...
Page 163
Pull-up resistor option registers (PU0, PU2 to PU7) These registers are used to set whether to use an on-chip pull-up resistor at each port or not. By setting PU0 and PU2 to PU7, the on-chip pull-up resistors of the ...
Page 164
Figure 6-25. Format of Pull-Up Resistor Option Register (PU0, PU2 to PU7) Address: FF30H After Reset: 00H Symbol 7 6 PU0 0 0 Address: FF32H After Reset: 00H Symbol 7 6 PU2 0 0 Address: FF33H After Reset: 00H Symbol ...
Page 165
Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as ...
Page 166
Selection of Mask Option The following mask option is provided in the mask ROM version. The flash memory versions have no mask options. Table 6-7. Comparison Between Mask ROM Version and Flash Memory Version Pin Name Note Mask option ...
Page 167
CHAPTER 7 CLOCK GENERATOR 7.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit ...
Page 168
Figure 7-1. Block Diagram of Clock Generator FRC Subsystem XT1 f XT clock oscillator XT2 Main system X1 clock f X2 oscillator X STOP 168 CHAPTER 7 CLOCK GENERATOR Internal bus Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 ...
Page 169
Clock Generator Control Registers The clock generator is controlled by the following two registers. • Processor clock control register (PCC) • Oscillation stabilization time select register (OSTS) (1) Processor clock control register (PCC) This register selects the CPU clock ...
Page 170
Figure 7-2. Format of Processor Clock Control Register (PCC) Address: FFFBH After reset: 04H Symbol <7> <6> PCC MCC FRC MCC 0 Oscillation possible 1 Oscillation stopped FRC 0 Internal feedback resistor used 1 Internal feedback resistor not used CLS ...
Page 171
The fastest instructions of the µ PD780024A, 780034A, 780024AY, and 780034AY Subseries are carried out in two CPU clocks. The relationship between the CPU clock (f in Table 7-2. Table 7-2. Relationship Between CPU Clock and Minimum Instruction Execution Time ...
Page 172
Oscillation stabilization time select register (OSTS) This register is used to select the oscillation stabilization time from when reset is effected or STOP mode is released to when oscillation is stabilized. OSTS is set by an 8-bit memory manipulation ...
Page 173
System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (8.38 MHz TYP.) connected to the X1 and X2 pins. External clocks can be input to the ...
Page 174
Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (32.768 kHz TYP.) connected to the XT1 and XT2 pins. External clocks can be input to the subsystem clock oscillator. In this case, input a clock signal ...
Page 175
CHAPTER 7 CLOCK GENERATOR Caution 1. When using the main system clock oscillator and subsystem clock oscillator, wire as follows in the area enclosed by broken lines in Figures 7-4 and 7-5 to avoid an adverse effect from wiring capacitance. ...
Page 176
Figure 7-6. Examples of Incorrect Oscillator Connection (2/2) (c) Wiring near high fluctuating current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, ...
Page 177
When subsystem clock is not used not necessary to use the subsystem clock for low power consumption operations and watch operations, connect the XT1 and XT2 pins as follows. XT1: Connect directly ...
Page 178
Clock Generator Operations The clock generator generates the following types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f X • Subsystem clock f XT • CPU clock f CPU • ...
Page 179
Main system clock operations When operating with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) cleared to 0), the following operations are carried out by PCC setting. (a) Because the operation-guaranteed instruction ...
Page 180
Subsystem clock operations When operating with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The minimum instruction execution time remains constant (122 µ ...
Page 181
System clock and CPU clock switching procedure This section describes procedure for switching between the system clock and CPU clock. Figure 7-9. System Clock and CPU Clock Switching V DD RESET Interrupt request signal System clock CPU clock <1> ...
Page 182
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.1 Functions of 16-Bit Timer/Event Counter 0 16-bit timer/event counter 0 has the following functions. (1) Interval timer 16-bit timer/event counter 0 generates interrupt requests at the preset time interval. • Number of counts: ...
Page 183
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.2 Configuration of 16-Bit Timer/Event Counter 0 16-bit timer/event counter 0 consists of the following hardware. Table 8-1. Configuration of 16-Bit Timer/Event Counter 0 Item Timer counter 16-bit timer counter 0 (TM0) Register 16-bit ...
Page 184
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (1) 16-bit timer counter 0 (TM0) TM0 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value ...
Page 185
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 CR00 is set by a 16-bit memory manipulation instruction. RESET input makes CR00 undefined. Cautions 1. Set CR00 to a value other than 0000H in the clear & start mode entered on a match ...
Page 186
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 CR01 is set by a 16-bit memory manipulation instruction. RESET input makes CR01 undefined. Caution Set CR01 to other than 0000H in the clear & start mode entered on a match between TM0 and ...
Page 187
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-2. Format of 16-Bit Timer Mode Control Register 0 (TMC0) Address: FF60H After reset: 00H Symbol <3> TMC0 TMC03 TMC03 TMC02 Operating mode and clear ...
Page 188
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) Capture/compare control register 0 (CRC0) This register controls the operation of the 16-bit timer capture/compare registers (CR00, CR01). CRC0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input clears CRC0 ...
Page 189
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (3) 16-bit timer output control register 0 (TOC0) This register controls the operation of the 16-bit timer/event counter output controller. It sets R-S type flip-flop (LV0) set/reset, output inversion enable/disable, and 16-bit timer/event counter ...
Page 190
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (4) Prescaler mode register 0 (PRM0) This register is used to set the 16-bit timer counter 0 (TM0) count clock and TI00, TI01 input valid edges. PRM0 is set by an 8-bit memory manipulation ...
Page 191
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (5) Port mode register 7 (PM7) This register sets port 7 input/output in 1-bit units. When using the P70/TO0/TI00 pin for timer output, clear PM70 and the output latch of P70 to 0. When ...
Page 192
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4 Operation of 16-Bit Timer/Event Counter 0 8.4.1 Interval timer operation Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-7 allows operation as an ...
Page 193
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-8. Interval Timer Configuration Diagram Noise TI00/TO0/P70 eliminator Note OVF0 is 1 only when 16-bit timer capture/compare register 00 ...
Page 194
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 When the compare register is changed during timer count operation, if the value after 16-bit timer capture/ compare register 00 (CR00) is changed is smaller than that of 16-bit timer counter 0 (TM0), TM0 ...
Page 195
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.2 External event counter operation The external event counter counts the number of external clock pulses to be input to the TI00 pin with using 16- bit timer counter 0 (TM0). TM0 is incremented ...
Page 196
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-12. External Event Counter Configuration Diagram Noise eliminator X Valid edge of TI00 Note OVF0 is 1 only when 16-bit timer capture/compare register 00 is set to FFFFH. Figure 8-13. ...
Page 197
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 8.4.3 Pulse width measurement operations It is possible to measure the pulse width of the signals input to the TI00 pin and TI01 pin using 16-bit timer counter 0 (TM0). There are two measurement ...
Page 198
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-15. Configuration Diagram for Pulse Width Measurement with Free-Running Counter TI00/TO0/P70 Figure 8-16. Timing of Pulse Width Measurement Operation with Free-Running Counter and ...
Page 199
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 (2) Measurement of two pulse widths with free-running counter When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 8-17 possible to simultaneously measure the pulse ...
Page 200
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0 Figure 8-18. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock TM0 count value 0000H 0001H TI00 pin input CR01 capture value INTTM01 TI01 pin input CR00 ...