ADMC326YR Analog Devices, ADMC326YR Datasheet
ADMC326YR
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ADMC326YR Summary of contents
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... ALU MAC SHIFTER REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
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ADMC326–SPECIFICATIONS ANALOG-TO-DIGITAL CONVERTER Parameter Signal Input 1 Resolution 2 Linearity Error 2 Zero Offset Channel-to-Channel Comparator Match Comparator Delay 2 ADC Hi-Level Input Current 2 ADC Lo-Level Input Current NOTES 1 Resolution varies with PWM switching frequency (double update mode) ...
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VOLTAGE REFERENCE Parameter Voltage Level (V ) REF Output Voltage Drift NOTES 1 This specification for voltage level ( for SOIC package only, at specified temperature range. REF Specifications subject to change without notice. POWER-ON RESET Parameter Reset ...
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ADMC326 TIMING PARAMETERS Parameter Clock Signals Signal t is defined as 0 The ADMC326 uses an input clock with a CK CKIN frequency equal to half the instruction rate MHz input clock (which is equivalent to ...
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Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to ...
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... Temperature Model Range ADMC326YR-xxx-yy – +105 C ADMC326TR-xxx-yy – +125 C ADMC326YN-xxx-yy – +105 C ADMC326TN-xxx-yy – +125 C NOTES xxx = customer identification code ROM identification code. To place an order for a custom ROM-coded ADMC326 processor, please request a copy of the ADMC ROM ordering package, available from your Analog Devices Sales representative ...
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GENERAL DESCRIPTION The ADMC326 is a low cost, single-chip DSP-based controller, suitable for permanent magnet synchronous motors, AC induction motors and brushless dc motors. The ADMC326 integrates a 20 MIPS, fixed-point DSP core with a complete set of motor control ...
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ADMC326 DSP CORE ARCHITECTURE OVERVIEW Figure overall block diagram of the DSP core of the ADMC326, which is based on the fixed-point ADSP-2171. The flexible architecture and comprehensive instruction set of the ADSP-2171 allow the processor to ...
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SPORT1 receive and transmit sections can generate unique interrupts on completing a data word transfer. • SPORT1 can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated ...
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ADMC326 shown in Figure 4. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors as shown in Figure 4. A parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output signal (CLKOUT) is generated ...
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Because this hardware shutdown mechanism is asynchro- nous, and the associated PWM disable circuitry does not use clocked logic, the PWM will shut down even if the DSP clock is not running. The PWM system may also be shut ...
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ADMC326 The largest value that can be written to the 16-bit PWMTM register is 0xFFFF = 65,535, which corresponds to a minimum PWM switching frequency of PWM,min 2 65 535 , for a CLKOUT frequency of ...
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The PWM is center-based. This means that in single update mode the resulting output waveforms are symmetrical and centered in the PWMSYNC period. Figure 7 presents a typical PWM tim- ing diagram illustrating the PWM-related registers’ (PWMCHA, PWMTM, PWMDT, and ...
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ADMC326 after the PWMCHA, PWMCHB, and PWMCHC registers, then the first PWMSYNC pulse (and interrupt if enabled) will be generated (1.5 t PWMTM) seconds after the initial CK write to the PWMTM register in single update mode. In double update ...
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For the situation illustrated in Figure 9, the appropriate value for the PWMSEG register is 0x00A7. In ECM operation, be- cause each inverter leg is disabled for certain periods of time, the PWMSEG register is changed based upon the position ...
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ADMC326 Table V. Fundamental Characteristics of PWM Generation Unit of ADMC326 16-BIT PWM TIMER Parameter Counter Resolution Edge Resolution (Single Update Mode) Edge Resolution (Double Update Mode) Programmable Dead Time Range Programmable Dead Time Increments Programmable Pulse Deletion Range Programmable ...
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CHARGING CAPACITOR – nF Figure 13. PWMSYNCWT Program Value ADC Resolution The ADC is intrinsically linked to the PWM block through the PWMSYNC pulse controlling the ADC conversion process. Because of ...
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ADMC326 TARGET RAMP V REF MINIMUM RAMP Figure 15. Current Ramp ADC Registers The configuration of all registers of the ADC System is shown at the end of the data sheet. AUXILIARY PWM TIMERS Overview The ADMC326 provides two variable ...
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Parameter Resolution PWM Frequency PWM DAC Equation The auxiliary PWM output can be filtered in order to produce a low frequency analog signal between 2-pole filter with a 1.2 kHz cutoff frequency will sufficiently at- tenuate ...
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ADMC326 If the serial port communications use an internally generated SCLK1, the PIO3/SCLK1 pin may be used as a general-purpose PIO line. When external SCLK mode is selected, the PIO/SCLK1 pin must be enabled as SCLK1 (PIOSELECT [3] = 0). ...
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... SCLK1, is still available in the alternate configuration. Development Tools Users are recommended to obtain the ADMCF326-EVALKIT from Analog Devices. The tool kit contains everything required to quickly and easily evaluate and develop applications using the ADMCF326 and ADMC326 DSP Motor Controllers. Please contact your ADI sales representative for ordering information. ...
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ADMC326 Address (HEX) Name 0x2000 ADC1 0x2001 ADC2 0x2002 ADC3 0x2003 ADCAUX 0x2004 PIODIR0 0x2005 PIODATA0 0x2006 PIOINTEN0 0x2007 PIOFLAG0 0x2008 PWMTM 0x2009 PWMDT 0x200A PWMPD 0x200B PWMGATE 0x200C PWMCHA 0x200D PWMCHB 0x200E PWMCHC 0x200F PWMSEG 0x2010 AUXCH0 0x2011 AUXCH1 ...
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A CHANNEL CROSSOVER CROSSOVER B CHANNEL CROSSOVER 1 = CROSSOVER C CHANNEL CROSSOVER Default bit values are shown; if ...
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ADMC326 LOW SIDE GATE CHOPPING 0 = DISABLE 1 = ENABLE HIGH SIDE GATE CHOPPING Figure 20. Configuration of ...
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ADMC326 Figure 22. Configuration of Additional PIO Registers Default bit values are shown value ...
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Default bit values are shown value ...
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ADMC326 Figure 24. Configuration of Additional AUX Registers Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are ...
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OFFSET MODE AUXILIARY 1 = INDEPENDENT MODE PWM SELECT ADC 0 = CLKIN RATE COUNTER 1 = CLKOUT RATE SELECT 1ST HALF OF PWM CYCLE ...
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ADMC326 0 = DISABLE 1 = ENABLE 15 0 INTERRUPT FORCE IRQ2 SOFTWARE 1 SOFTWARE 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 TIMER PERIPHERAL (OR IRQ2 DISABLE (MASK) ...
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DISABLED SPORT1 ENABLE 1 = ENABLED Default bit values are shown value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field. PIN 1 0.250 (6.35) MAX 0.200 (5.05) ...