HY5S7B2LFP-H Hynix Semiconductor, HY5S7B2LFP-H Datasheet
HY5S7B2LFP-H
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HY5S7B2LFP-H Summary of contents
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MOBILE SDR SDRAMs based 4Bank x32 I/O 512M (16Mx32bit) Mobile SDRAM - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume ...
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Document Title 4Bank 32bits Synchronous DRAM Revision History Revision No. 0.1 Initial Draft Defined : IDD value (page 11 ~ 12) 0.2 Correct : CAPACITANCE (Page 10 : Data input/output capacitance) Before spec. : 3.5min ~ 6.0max ...
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DESCRIPTION The Hynix HY5S7B2LF(P) is suited for non-PC application which use the batteries such as PDAs, 2.5G and 3G cellular phones with internet access and multimedia capabilities, mini-notebook, handheld PCs. The Hynix 512M Mobile SDRAM is 536,870,912-bit CMOS Mobile Synchronous ...
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INFORMATION for Hynix KNOWN GOOD DIE With the advent of Mullti-Chip package (MCPs), Package on Package (PoP) and system in a package (SiP) applications, customer demand for Known Good Die (KGD) has increased. Requirements for smaller form factors and higher ...
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... Package Type : 90ball, 0.8mm pitch FBGA (Lead Free, Lead [mm ● HY5S7B2LFP : Lead Free HY5S7B2LF : Leaded 512M SDRAM ORDERING INFORMATION Part Number HY5S7B2LF-H HY5S7B2LF-S HY5S7B2LFP-H HY5S7B2LFP-S Rev 1.0 / Jan. 2007 512Mbit (16Mx32bit) Mobile SDR Memory = 1.8V 1.8V DDQ o C CAS Clock Frequency ...
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BALL DESCRIPTION VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 A8 VSS Rev 1.0 / Jan. 2007 512Mbit (16Mx32bit) Mobile SDR Memory ...
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BALL DESCRIPTION Ball Out SYMBOL F2 CLK F3 CKE G9 CS G7,G8 BA0, BA1 H7, H8, J8, J7, J3, J2, H3, H2 A12 H1, G3, H9, G2, G1 F8, F7, F9 RAS, CAS, WE F1, E8 UDQM, LDQM ...
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ABSOLUTE MAXIMUM RATING Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative to V Voltage on V relative Voltage on V relative to V DDQ SS Short Circuit Output Current Power Dissipation . Soldering Temperature ...
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CAPACITANCE ( f=1MHz) Parameter Input capacitance Data input/output capacitance DC CHARACTERRISTICS I Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Note : 1.8V. All other ...
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DC CHARACTERISTICS II Parameter Symbol Operating Current IDD1 IDD2P Precharge Standby Current in Power Down Mode IDD2PS IDD2N Precharge Standby Current in Non Power Down Mode IDD2NS IDD3P Active Standby Current in Power Down Mode IDD3PS IDD3N Active Standby Current ...
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DC CHARACTERISTICS III Temp Banks 45 280 85 550 Notes: 1. VDD / VDDQ = 1.8V 2. Related numerical values in this 45 3. With a on-chip temperature sensor of Mobile memory, auto temperature compensated self ...
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AC CHARACTERISTICS I Parameter System Clock Cycle Time CAS Latency=3 Clock High Pulse Width Clock Low Pulse Width Access Time From Clock CAS Latency=3 Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time CKE ...
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AC CHARACTERISTICS II Parameter RAS Cycle Time RAS to CAS Delay RAS Active Time RAS Precharge Time RAS to RAS Bank Active Delay AUTO REFRESH Period CAS to CAS Delay Write Command to Data-In Delay Data-in to Precharge Command Data-In ...
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FUNCTIONAL BLOCK DIAGRAM 4Mbit x 4banks x 32 I/O Mobile Synchronous DRAM xten ister ctive ...
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BASIC FUNCTIONAL DESCRIPTION Mode Register BA1 BA0 A12 A11 A10 Code A9 Write Mode 0 Burst Read and Burst Write 1 Burst Read and Single Write CAS Latency CAS Latency 0 ...
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BASIC FUNCTIONAL DESCRIPTION Extended Mode Register BA1 BA0 A12 A11 (Driver Strength Driver Strength 0 0 Full 0 1 1/2 Strength 1 0 1/4 Strength 1 1 Reserved Rev 1.0 / Jan. 2007 ...
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COMMAND TRUTH TABLE Function CKEn-1 Mode Register Set Extended Mode Register Set No Operation Device Deselect Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst stop Data Write/Output Enable Data Mask/Output Disable ...
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CURRENT STATE TRUTH TABLE Current State CS RAS CAS Idle ...
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CURRENT STATE TRUTH TABLE Current State CS RAS CAS WE Read Write ...
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CURRENT STATE TRUTH TABLE Current State CS RAS CAS Precharging ...
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CURRENT STATE TRUTH TABLE Current State CS RAS CAS WE Write Recovering Write Recovering with Auto ...
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Note : 1. H: Logic High, L: Logic Low, X: Don 2. All entries assume that CKE was active during the preceding clock cycle both banks are idle and CKE is inactive, then in power down cycle 4. ...
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CKE Enable(CKE) Truth TABLE CKE Current Previous Current State Cycle Cycle Self Refresh Power Down Deep ...
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CKE Enable(CKE) Truth TABLE CKE Current Previous Current State Cycle Cycle All Banks H L Idle Any State ...
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Mobile SDR SDRAM OPERATION State Diagram Power On Precharge All Bank (E)MRS (EXTENDED) Mode Register Set DEEP POWER DOWN READA SUSPEND READ with AP Read Read READ READ SUSPEND Automatic Sequence Manual input Rev 1.0 / Jan. 2007 512Mbit (16Mx32bit) ...
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DESELECT The DESELECT function (CS = High) prevents new commands from being executed by the Mobile SDRAM, the Mobile SDRAM ignore command input at the clock. However, the internal status is held. The Mobile SDRAM is effectively dese- lected. Operations ...
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READ / WRITE COMMAND Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACT) command. An interval of tRCD is required between the bank active command input and ...
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READ A read operation starts when a read command is input. Output buffer becomes Low-Z in the (/CAS Latency - 1) cycle after read command set. The SDRAM can perform a burst read operation. The burst length can be set ...
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READ to READ Data from a read burst may be concatenated or truncated by a subsequent READ command. The first data from the new burst follows either the last element of a completed burst or the last desired element of ...
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CLK Command READ BA, Col Address (or ): Data out from column n n (b) 2) BA, Col = Bank A, Column n (b) 3) Burst Length = 4 ...
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READ BURST TERMINATE Data from any READ burst may be truncated with a BURST TERMINATE command. The BURST TERMINATE latency is equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued X cycles after the READ ...
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READ to WRITE Data from READ burst must be completed or truncated before a subsequent WRITE command can be issued. If trun- cation is necessary, the BURST TERMINATE command must be used, as shown in next fig. CLK Com m ...
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READ to PRECHARGE Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In ...
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Write Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data given DM signal is registered Low, the corresponding data will be written ...
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WRITE to WRITE Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data, can be maintained. The new WRITE command can be issued on any ...
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WRITE to READ CLK Command WRITE BA, Col Address The preceding burst write operation can be aborted and a new burst read operation can be ...
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WRITE to PRECHARGE Data for any WRITE burst may be followed by a subsequent PRECHARGE command to the same bank (provided Auto Precharge was not activated). When the precharge command is executed for the same bank as the write command ...
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BURST TERMINATE The BURST TERMINATE command is used to truncate read bursts (with autoprecharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation sec- tion of this datasheet. ...
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PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. Another command to the same bank (or banks) being precharged must not be issued until the precharge time ...
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AUTO REFRESH AND SELF REFRESH Mobile SDRAM devices require a refresh of all rows in any rolling 64ms interval. Each refresh is generated in one of two ways explicit AUTO REFRESH command internally timed event ...
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CLK CKE High-Z CS RAS CAS A11, 12 BA0, 1 AUTO REFRESH COMMAND Note 1: If all banks are in the idle status and CKE is inactive (low level), the self refresh mode is set. Function ...
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MODE REGISTER SET The mode registers are loaded via the address bits. BA0 and BA1 are used to select between the Mode Register and the Extended Mode Register. See the Mode Register description in the register definition section. The MODE ...
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POWER DOWN Power down occurs if CKE is set low coincident with Device Deselect or NOP command and when no accesses are in progress. If power down occurs when all banks are idle Precharge Power Down. If Power ...
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CLK CKE COMMAND NOP All banks idle Enter power-down mode. CLK CKE PCG NOP COMMAND Pre-charge all Rev 1.0 / Jan. 2007 512Mbit (16Mx32bit) Mobile SDR Memory Input buffers gated off Exit power-down mode. tCKS NOP Input buffers gated off ...
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CLK tCKS tCKH CKE tCMS tCMH PRECHARGE COMMAND DQM A0- A9,Amax ALL BANKS A10 SINGLE BANK tAS tAH BANKS BA0, BA1 High-Z DQ Precharge all active banks Rev 1.0 / Jan. 2007 512Mbit (16Mx32bit) Mobile SDR Memory tCK tCH tCL ...
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Power-up and Initialization Like a Synchronous DRAM, Low Power SDRAM(Mobile SDRAM) must be powered up and initialized in a predefined man- ner. Power must be applied to V After power up, an initial pause of 200 usec is required. And ...
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Precharge The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge command is issued with address A10, high, then all banks will be precharged, and If ...
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Clock Suspend The Clock Suspend command is used to suspend the internal clock of Mobile SDRAM. The clock suspend operation stops transmission of the clock to the internal circuits of the device during burst transfer of data to stop the ...
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Power Down The Power Down command is used to reduce standby current. Before this command is issued, all banks must be pre- charged and tRP must be passed after a precharge command. Once the Power Down command is initiated by ...
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Special Operation for Low Power Consumption Deep Power Down Mode Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the devices. Data will not be retained ...
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Deep Power Down Mode (Continued) Deep Power Down Mode Exit Sequence The Deep Power Down mode is exited by asserting CKE high. After the exit, the following sequence is needed to enter a new command. 1. Maintain NOP input conditions ...
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PACKAGE INFORMATION 90 Ball FBGA 0.8mm pitch (Size 10.0mm x 13.0mm) 0.90. 1.80 Rev 1.0 / Jan. 2007 512Mbit (16Mx32bit) Mobile SDR Memory 10.00 Typ. 0.8Typ. Bottom View 6.40 Typ. 11 HY5S7B2LF(P) Series A1 INDEX MARK 1.80 Unit [mm] 0.80 ...