PALLV16V8-10JC Lattice Semiconductor Corp., PALLV16V8-10JC Datasheet
PALLV16V8-10JC
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PALLV16V8-10JC Summary of contents
Page 1
... The PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable CMOS technology functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the exception of the PAL16C1. The PALLV16V8Z provides zero standby power and high speed. At 30- A maximum standby current, the PALLV16V8Z allows battery powered operation for an extended period ...
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... FUNCTIONAL DESCRIPTION The PALLV16V8 is a low-voltage, EE CMOS version of the PALCE16V8. The PALLV16V8Z is a low-voltage, EE CMOS version of the PALCE16V8. In addition, the PALLV16V8Z has zero standby power and an unused product term disable feature for reduced power consumption. The PALLV16V8 is a universal PAL device. It has eight independently configurable macrocells ...
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... The user is given two design options with the PALLV16V8. First, it can be programmed as a standard PAL device from the PAL16R8 and PAL10H8 series. The PAL programmer manufacturer will supply device codes for the standard PAL device architectures to be used with the PALLV16V8. ...
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... Q on the register. The output buffer is enabled by OE. Combinatorial Configurations The PALLV16V8 has three combinatorial output configurations: dedicated output in a non- registered device, I non-registered device and I registered device. Dedicated Output In a Non-Registered Device The control bit settings are SG0 = 1, SG1 = 0 and SL0 the OR gate ...
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... It can also save “DeMorganizing” efforts. Selection is through a programmable bit SL1 of the AND/OR logic. The output is active high if SL1 PALLV16V8-10 and PALLV16V8Z-20 Families Table 1. Macrocell Configuration Devices Emulated ...
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... Combinatorial output active low Notes: . Feedback is not available on pins 15 and 16 in the combinatorial output mode. . The dedicated-input configuration is not available on pins 15 and 16. 6 PALLV16V8-10 and PALLV16V8Z-20 Families OE b. Registered active high d. Combinatorial I/O active high Note 1 f. Combinatorial output active high g. Dedicated input Figure 2. Macrocell Confi ...
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... The preload function is not disabled by the security bit. This allows functional testing after the security bit is programmed. Security Bit A security bit is provided on the PALLV16V8 as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. However, programming and verifi ...
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... Product-Term Disable On a programmed PALLV16V8Z, any product terms that are not used are disabled. Power is cut off from these product terms so that they do not draw current. As shown in the I graph, product-term disabling results in considerable power savings. This saving is greater at the higher frequencies ...
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... CLK PALLV16V8-10 and PALLV16V8Z-20 Families SL0 7 SG1 SL1 SL0 SG1 SL1 SL0 ...
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... GND 10 10 PALLV16V8-10 and PALLV16V8Z-20 Families CLK SL0 3 SG1 SL1 SL0 2 SG1 SL1 SL0 1 ...
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... (Note 2) OUT 0 Max (Note 3) OUT CC Outputs Open ( mA Max MHz (Note 4) OUT CC and I (or I and I ). OZL IL OZL CC PALLV16V8-10 (Com’ Min Max I = – – 100 mA 0.2 OL 2.0 5.5 ...
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... MHz V = 2.0 V OUT Parameter Description LOW HIGH External Feedback 1/( Internal Feedback (fCNT 1/( Feedback 1/( can be found using the following equation: CF PALLV16V8-10 (Com’l) Typ Unit -10 Min Max Unit 71.4 MHz 83.3 MHz 83 ...
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... 0 Max (Note 3) OUT CC Outputs Open ( mA) OUT V = Max MHz (Note 4) CC and I (or I and I ). OZL IH OZH vs. frequency graph for typical measurements. CC PALLV16V8Z-20 (Ind - + with CC Min Max I = – –75 µA V – 100 µA ...
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... MHz V = 2.0 V OUT Parameter Description LOW HIGH External Feedback 1/( Internal Feedback (fCNT) 1/( Feedback 1/( can be found using the following equation: CF PALLV16V8Z-20 (Ind) Typ Unit 5 = 25° -20 Min Max Unit MHz 50 MHz 66.7 MHz will typically be about 2 ns faster ...
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... Clock width OE Output Notes 1.5 V for input signals and V /2 for output signals Input pulse amplitude 3 Input rise and fall times typical. PALLV16V8-10 and PALLV16V8Z-20 Families Input or Feedback Clock V TO Registered Output 17713D-7 Input V T Output ...
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... Open PZX Closed H Z: Open PXZ Closed 16 PALLV16V8-10 and PALLV16V8Z-20 Families INPUTS OUTPUTS Must be Will be Steady Steady May Change Changing from from May Change Changing from from Don’t Care, Changing, ...
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... Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 50% of the device, a midpoint is defined for I to estimate the I requirements for a particular design. CC PALLV16V8-10 and PALLV16V8Z-20 Families Frequency (MHz ...
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... Max Reprogramming Cycles ROBUSTNESS FEATURES The PALLV16V8 has some unique features that make it extremely robust, especially when operating in high-speed design environments. Pull-up resistors on inputs and I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise fi ...
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... POWER-UP RESET The PALLV16V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization ...
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... Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, tests on packages are performed in a constant temperature. Therefore, the measurements can only be used similar environment. 20 PALLV16V8-10 and PALLV16V8Z-20 Families Parameter Description 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air measurement relative to a specifi ...
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... I I GND 10 OE/I PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output Connect V = Supply Voltage CC PALLV16V8-10 and PALLV16V8Z-20 Families 17713D-2 Note: Pin 1 is marked for orientation. PLCC I I ...
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... PD Valid Combinations PALLV16V8-10 PC, JC, SC PALLV16V8Z-20 PI PALLV16V8-10 and PALLV16V8Z-20 Families - Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Vantis sales office to confirm availability of specific valid combinations and to check on newly released ...