K4N56163QG-ZC25 Samsung, K4N56163QG-ZC25 Datasheet
K4N56163QG-ZC25
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K4N56163QG-ZC25 Summary of contents
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... K4N56163QG 256Mbit gDDR2 SDRAM Notice INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4N56163QG Revision History Revision Month Year 0.0 October 2005 1.0 January 2006 1.1 April 2006 1.2 July 2006 1.3 October 2006 1.4 December 2006 Defined Target Specification Defined Final Specification - Added current spec. - Deleted -ZC33(300Mhz) spec. - Added -ZC20(500Mhz) preliminary spec. - Corrected typo. - Added comment on page 33. - Corrected typo on page 5(package information). ...
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... Write Latency (WL) = Read Latency (RL) -1 2.0 ORDERING INFORMATION Part NO. K4N56163QG-ZC20 K4N56163QG-ZC22 K4N56163QG-ZC25 K4N56163QG-ZC2A * K4N56163QG-GC is the Leaded part number. 3.0 GENERAL DESCRIPTION FOR 4M x 16Bit x 4 Bank gDDR2 SDRAM The 256Mb gDDR2 SDRAM chip is organized as 4Mbit x 16 I/O x 4banks banks device. This synchronous device achieve high speed graphic double-data-rate transfer rates 1000Mb/sec/pin for general applications ...
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... K4N56163QG 4.0 PIN CONFIGURATION Normal Package (Top View) UDQ6 VDDQ UDQ4 VDD LDQ6 VDDQ LDQ4 VDDL Note : VDDL and VSSDL are power and ground for the DLL recommended that they are isolated on the device from VDD, VDDQ, VSS, and VSSQ. Ball Locations ...
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... K4N56163QG 5.0 PACKAGE DIMENSIONS (84 Ball FBGA 84- ∅ 0.45± ∅0 #A1 11.00 ± 0.10 6.40 0.80 1. 3.20 (5.5) (0.90) 0.05 (1.80) 11.00 ± 0.10 - 5/64 - 256M gDDR2 SDRAM # A1 INDEX MARK (OPTIONAL) 0.35± 0.05 MAX.1.20 Unit : mm Rev. 1.4 Dec. 2006 ...
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... K4N56163QG 6.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION Symbol Type Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the posi- CK, CK Input tive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). ...
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... K4N56163QG 7.0 ABSOLUTE MAXIMUM DC RATINGS Symbol V Voltage on V pin relative to Vss Voltage on V pin relative to Vss DDQ DDQ V Voltage on V pin relative to Vss DDL DDL V V Voltage on any pin relative to Vss IN, OUT T Storage Temperature STG Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... K4N56163QG 8.4 AC Input Test Conditions Symbol V Input reference voltage REF V Input signal maximum peak to peak swing SWING(MAX) SLEW Input signal minimum slew rate Note : 1. Input waveform timing is referenced to the input signal crossing through the V 2. The input signal minimum slew rate maintained over the range from V max for falling edges as shown in the below figure ...
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... K4N56163QG 8.7 OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Notes: 1. Absolute Specifications (0°C ≤ T ≤ +95°C; V CASE 2. Impedance measurement condition for output source dc current: V values of VOUT between V and V DDQ DDQ VOUT/Iol must be less than 23 ...
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... Refresh to active/Refresh command time Average periodic refresh interval 9.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS SPEED Bin (CL-tRCD-tRP) Parameter CAS LATENCY tCK tRCD tRP tRC tRAS K4N56163QG-ZC25 Frequency Cas Latency 400MHz ( 2.5ns ) 6 350MHz (2.86ns ) 5 300MHz (3.3ns ) 5 K4N56163QG-ZCA Frequency Cas Latency 350MHz ( 2 ...
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... K4N56163QG 9.3 Timing Parameters by Speed Grade Parameter DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width CK half period Clock cycle time, CL and DM input hold time DQ and DM input setup time Control & Address input pulse width for each input ...
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... K4N56163QG Parameter CAS to CAS command delay Write recovery time Auto precharge write recovery + pre- charge time Internal write to read command delay Internal read to precharge command delay Exit self refresh to a non-read command Exit self refresh to a read command Exit precharge power down to any non- ...
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... K4N56163QG 2. gDDR2 SDRAM AC timing reference load Following figure represents the timing reference load used in defining the relevant timing parameters of the part not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment ...
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... K4N56163QG 5. AC timings are for linear signal transitions. 6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 7. All voltages are referenced to VSS. 8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified ...
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... K4N56163QG 18. tIS and tIH (input setup and hold) derating 1) Input waveform timing is referenced from the input signal crossing at the V the device under test. 2) Input waveform timing is referenced from the input signal crossing at the V the device under test. 2.0 V/ns ∆tIS 4.0 +150 3.5 +143 3.0 +133 2 ...
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... K4N56163QG 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. MIN ( tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) ...
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... K4N56163QG 29. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V ential data strobe crosspoint for a rising signal, and from the input signal crossing at the V falling signal applied to the device under test. 30. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V ential data strobe crosspoint for a rising signal and V test ...
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... K4N56163QG Device Operation & Timing Diagram 256M gDDR2 SDRAM - 18/64 - Rev. 1.4 Dec. 2006 ...
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... K4N56163QG Functional Description Simplified State Diagram OCD calibration Setting MRS EMRS CKEL Active Power Down Write Writing WRA Writing with Autoprecharge Note : Use caution with this diagram indented to provide a floorplan of the possible state transitions and the commands to control them, not all details. In particular situations involving more than one bank, enabling/disabling on-die termination, Power Down entry/ exit - among other things - are not captured in full detail ...
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... K4N56163QG Basic Functionality Read and write accesses to the gDDR2 SDRAM are burst oriented; accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0, BA1 select the bank ...
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... K4N56163QG Initialization Sequence after Power Up tCH tCL CK /CK tIS V IH (ac) CKE ODT PRE Command NOP EMRS ALL tRP 400ns DLL ENABLE Programming the Mode Register For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time(tWR) are user defined variables and must be programmed with a Mode Register Set (MRS) command ...
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... K4N56163QG gDDR2 SDRAM Mode Register Set (MRS) The mode register stores the data for controlling the various operating modes of gDDR2 SDRAM. It controls CAS latency, burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make gDDR2 SDRAM useful for various applications. ...
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... K4N56163QG gDDR2 SDRAM Extended Mode Register Set EMRS(1) The extended mode register(1) stores the data for enabling or disabling the DLL, output driver strength, ODT value selection and addi- tive latency. The default value of the extended mode register is not defined, therefore the extended mode register must be written after power-up for proper operation ...
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... K4N56163QG EMRS (1) Programming BA1 BA0 A12 A11 0 1 Qoff 0 BA1 BA0 MRS mode 0 0 MRS 0 1 EMRS( EMRS(2): Reserved 1 1 EMRS(3): Reserved A10 (DQS Enable) 0 (Enable) 1 (Disable) A12 a Qoff (Optional) 0 Output buffer enabled 1 Output buffer disabled a. Outputs disabled - DQs, DQSs, DQSs . ...
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... K4N56163QG EMRS (2) Programming BA1 BA0 A12 A11 A10 * BA1 BA0 MRS mode 0 0 MRS 0 1 EMRS( EMRS( EMRS(3): Reserved *1 : The rest bits in EMRS(2) is reserved for future use and all bits except A0, A1, A2, A7and BA0, BA1, must be programmed to 0 when setting the mode register during initialization ...
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... K4N56163QG Off-Chip Driver (OCD) Impedance Adjustment gDDR2 SDRAM supports driver calibration feature and the flow chart below is an example of sequence. Every calibration mode com- mand should be followed by “OCD calibration mode exit” before any other command being issued. MRS should be set before entering OCD impedance adjustment and ODT (On Die Termination) should be carefully controlled depending on system environment ...
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... K4N56163QG Extended Mode Register Set for OCD impedance adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by gDDR2 SDRAM and drive of DQS is dependent on EMRS bit enabling DQS operation. In Drive(1) mode, all DQ, DQS signals are driven high and all DQS signals are driven low ...
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... K4N56163QG OCD adjust mode CMD EMRS NOP DQS_in DQ_in DM Drive Mode Drive mode, both Drive(1) and Drive(0), is used for controllers to measure gDDR2 SDRAM Driver impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers are turned-off tOIT after “OCD calibration mode exit” com- mand as the following timing diagram ...
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... K4N56163QG ODT (On Die Termination) On Die Termination (ODT feature that allows a DRAM to turn on/off termination resistance. For x16 configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices ...
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... K4N56163QG ODT timing for active/standby mode CKE (AC) IH ODT Internal Term Res. ODT timing for powerdown mode CKE (AC) IH ODT Internal Term Res. t AONPD,min t AONPD,max (AC AOND t AON,min (AC AOFPD,min - 30/64 - 256M gDDR2 SDRAM ...
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... K4N56163QG ODT timing mode switch at entering power down mode T CKE Entering Slow Exit Active Power Down Mode or Precharge Power Down Mode. ODT Internal Term Res. ODT Internal Term Res. ODT Internal Term Res. ODT Internal Term Res. T-4 T-3 T-2 T-1 t ANPD ...
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... K4N56163QG ODT timing mode switch at exiting power down mode (AC) IH CKE Exiting from Slow Active Power Down Mode or Precharge Power Down Mode. Active & Standby mode timings to be applied. Power Down mode tim- ings to be applied. Active & Standby mode timings to be applied ...
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... K4N56163QG Bank Activate Command Posted CAS operation is supported to make command and data bus efficient for sustainable bandwidths in gDDR2 SDRAM. In this operation, the gDDR2 SDRAM allows a CAS read or write command to be issued immediately after the RAS bank activate command (or any time during the RAS-CAS-delay time, tRCD, period). The command is held for the time of the Additive Latency (AL) before it is issued inside the device ...
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... K4N56163QG Posted CAS Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). The parameters that define how the burst mode will operate are burst sequence and burst length. gDDR2 SDRAM supports 4 bit burst and 8 bit burst modes only. For 8 bit burst mode, full interleave address ordering is supported, however, sequential address order- ing is nibble based for ease of implementation ...
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... K4N56163QG Burst Mode Operation The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL) ...
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... K4N56163QG Burst Read Command The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to ( -1) ...
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... K4N56163QG Burst Read Operation ( and CK/CK CAS CMD NOP READ A DQS DQs Burst Read followed by Burst Write (RL- CK/CK Post CAS CMD NOP READ A DQS DQ’s The minimum time from the burst read command to the burst write command is defined by a read-to-write-turn-around-time, which is 4 clocks in case operation, 6 clocks in case operation ...
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... K4N56163QG T0 T1 CK/CK Post CAS CMD NOP READ A0 DQS DQs The seamless burst read operation is supported by enabling a read command at every other clock for operation, and every 4 clock for operation. This operation is allowed regardless of same or different banks as long as the banks are activated. ...
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... K4N56163QG Burst Write Operation The Burst Write command is initiated by having CS, CAS and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is defined by a read latency (RL) minus one and is equal to ( -1);and is the number of clocks of delay that are required from the time the write command is registered to the clock edge associated to the first DQS strobe ...
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... K4N56163QG Burst Write Operation tWR = 2 (AL=0, CL=3 CK/CK CAS NOP CMD WRITE A DQS DQs Burst Write followed by Burst Read (AL=2, CL=3 tWTR = CK/CK Write to Read = BL/2 + tWTR NOP CMD NOP DQS DOUT A The minimum number of clock from the burst write command to the burst read command is [ BL/2 + tWTR]. This tWTR is not a write recovery time (tWR) but the time required to transfer the 4bit write data from the input buffer into sense amplifiers in the array ...
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... K4N56163QG Seamless Burst Write Operation BL CK/CK Post CAS CMD NOP WRITE A0 DQS DQ’s The seamless burst write operation is supported by enabling a write command every other clock for operation, every four clocks for operation. This operation is allowed regardless of same or different banks as long as the banks are activated. ...
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... K4N56163QG Write data mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on gDDR2 SDRAMs, Consistent with the implementation on gDDR SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to insure matched system timing x16 bit organization is not used during read cycles. ...
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... K4N56163QG Precharge Command The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank independently or all banks simultaneously. Three address bits A10, BA0 and BA1 for 256Mb are used to define which bank to pre- charge when the command is issued ...
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... K4N56163QG Example 2: Burst Read Operation Followed by Precharge RTP T0 CK/CK Post CAS CMD READ A DQS DQ’s first 4-bit prefetch Example 3: Burst Read Operation Followed by Precharge : RTP T0 CK/CK Posted CAS CMD READ A DQS DQ’s <= 2 clocks ...
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... K4N56163QG Example 4: Burst Read Operation Followed by Precharge : RTP T0 CK/CK Post CAS CMD READ A DQS DQ’s Example 5: Burst Read Operation Followed by Precharge : RTP T0 CK/CK Post CAS CMD READ A DQS DQ’s first 4-bit prefetch * : rounded to next integer < ...
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... K4N56163QG Burst Write followed by Precharge Minimum Write to Precharge Command spacing to the same bank = WL + BL/2 clks + tWR For write cycles, a delay must be satisfied from the completion of the last burst write cycle until the Precharge Command can be issued. This delay is known as a write recovery time (tWR) referenced from the completion of the burst write to the precharge command ...
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... K4N56163QG Auto-Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the gDDR2 SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle ...
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... K4N56163QG Example 1: Burst Read Operation with Auto Precharge RTP CK/CK Post CAS CMD NOP NOP READ A Autoprecharge AL + BL/2 clks DQS DQ’s second 4-bit prefetch first 4-bit prefetch Example 2: Burst Read Operation with Auto Precharge ...
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... K4N56163QG Example 3: Burst Read with Auto Precharge Followed by an activation to the Same Bank (tRC Limit ( internal tRCD = CK/CK A10 = 1 Post CAS CMD NOP READ A DQS DQ’s Example 4: Burst Read with Auto Precharge Followed by an Activation to the Same Bank ...
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... K4N56163QG Burst Write with Auto-Precharge If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The gDDR2 SDRAM automatically begins precharge operation after the completion of the burst write plus write recovery time (tWR). The bank undergoing auto-precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. ...
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... K4N56163QG Precharge & Auto Precharge Clarification From Command Precharge ( to same Bank as Read w/AP) Read w/AP Precharge All Precharge ( to same Bank as Write w/AP) Write w/AP Precharge All Precharge ( to same Bank as Precharge) Precharge Precharge All Precharge Precharge All Precharge All Note : 1. The value of tRTP is decided by the equation : max( RU<tRTP/tCK>, 2) where RU stands for round up. This is required to cover the max tCK case, which ...
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... K4N56163QG Self Refresh Operation The gDDR2 SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command is defined by hav- ing CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. ODT must be turned off before issuing Self Refresh command, by either driving ODT pin low or using EMRS command ...
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... K4N56163QG Power-Down Power-down is synchronously entered when CKE is registered low (along with Nop or Deselect command). CKE is not allowed to go low while mode register or extended mode register command time, or read or write operation is in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or autoprecharge, or auto-refresh is in progress, but power-down IDD spec will not be applied until finishing those operations ...
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... K4N56163QG If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK, ODT and CKE. Also the DLL is disabled upon entering precharge power- down or slow exit active power-down, but the DLL is kept enabled during fast exit active power-down ...
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... K4N56163QG Read to power down entry CMD RD BL=4 CKE DQ DQS DQS CMD RD BL=8 CKE DQ DQS DQS Read with Autoprecharge to power down entry CMD RDA BL=4 CKE DQ DQS DQS CMD RDA BL=8 CKE DQ DQS DQS Tx Tx+1 Tx+2 Tx+3 Tx+4 Read operation starts with a read command and CKE should be kept high until the end of burst operation ...
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... K4N56163QG Write to power down entry CMD WR BL=4 CKE DQ DQS DQS CMD WR BL=8 CKE DQ DQS DQS Write with Autoprecharge to power down entry CMD WRA BL=4 CKE DQ DQS DQS CMD WRA BL=8 CKE DQ DQS DQS Tm+1 Tm+2 Tm tWTR Tm+1 Tm+2 Tm+3 Tm ...
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... K4N56163QG Refresh command to power down entry CMD REF CKE Active command to power down entry CMD ACT CKE Precharge/Precharge all command to power down entry PR or CMD PRA CKE MRS/EMRS command to power down entry CMD MRS or EMRS CKE tMRD Asynchronous CKE Low Event DRAM requires CKE to be maintained “ ...
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... K4N56163QG Input Clock Frequency Change during Precharge Power Down gDDR2 SDRAM input clock frequency can be changed under following condition : gDDR2 SDRAM is in precharged power down mode. ODT must be turned off and CKE must be at logic LOW level. A minimum of 2 clocks must be waited after CKE goes LOW before clock frequency may change. SDRAM input clock frequency is allowed to change only within minimum and maximum operating frequency specified for the particular speed grade ...
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... K4N56163QG Command Truth Table Function Previous Cycle (Extended) Mode Register Set Refresh (REF) Self Refresh Entry Self Refresh Exit Single Bank Precharge Precharge all Banks Bank Activate Write Write with Auto Precharge Read Read with Auto-Precharge No Operation Device Deselect Power Down Entry ...
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... K4N56163QG Clock Enable (CKE) Truth Table for Synchronous Transitions 2 Current State Previous Cycle (N-1) L Power Down L L Self Refresh L Bank(s) Active H H All Banks Idle H H Note : 1. CKE (N) is the logic state of CKE at clock edge N; CKE (N–1) was the state of CKE at the previous clock edge. ...
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... K4N56163QG Input Signal Overshoot/Undershoot Specification AC Overshoot/Undershoot Specification for Address and Control Pins A0-A15, BA0-BA2, CS, RAS, CAS, WE, CKE, ODT Parameter Maximum peak amplitude allowed for overshoot area (See following figyre): Maximum peak amplitude allowed for undershoot area (See following figure): Maximum overshoot area above VDD (See following figure). ...
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... K4N56163QG Table 1. Full Strength Default Pulldown Driver Characteristics Minimum Voltage (V) (23.4 Ohms) 0.2 8.5 0.3 12.1 0.4 14.7 0.5 16.4 0.6 17.8 0.7 18.6 0.8 19.0 0.9 19.3 1.0 19.7 1.1 19.9 1.2 20.0 1.3 20.1 1.4 20.2 1.5 20.3 1.6 20.4 1.7 20.6 1.8 1.9 Figure 1. gDDR2 Default Pulldown Characteristics for Full Strength Driver 120 100 0.2 0.4 0.3 0.5 Pulldown Current (mA) Nominal Default Low (18 ohms) 11.3 16.5 21.2 25.0 28.3 30.9 33.0 34.5 35.5 36.1 36.6 36.9 37.1 37.4 37.6 37.7 37.9 0.6 0.8 1.0 1.2 0.7 0.9 1.1 1.3 VOUT to VSSQ (V) - 62/64 - 256M gDDR2 SDRAM Nominal Default High(18 ohms) (12.6 Ohms) 11.8 16.8 22.1 27.6 32.4 36.9 40.9 44.6 47.7 50.1 52.2 54.2 55.9 57.1 58.4 59.6 60.9 Maximum ...
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... K4N56163QG Table 2. Full Strength Default Pullup Driver Characteristics Minimum Voltage (V) (23.4 Ohms) 0.2 -8.5 0.3 -12.1 0.4 -14.7 0.5 -16.4 0.6 -17.8 0.7 -18.6 0.8 -19.0 0.9 -19.3 1.0 -19.7 1.1 -19.9 1.2 -20.0 1.3 -20.1 1.4 -20.2 1.5 -20.3 1.6 -20.4 1.7 -20.6 1.8 1.9 Figure 2. gDDR2 Default Pullup Characteristics for Full Strength Output Driver 0 -20 -40 -60 -80 -100 -120 0.2 0.4 0.3 0.5 Pulldown Current (mA) Nominal Default Low (18 ohms) -11.1 -16.0 -20.3 -24.0 -27.2 -29.8 -31.9 -33.4 -34.6 -35.5 -36.2 -36.8 -37.2 -37.7 -38.0 -38.4 -38.6 0.6 0.8 1.0 1.2 0.7 0.9 1.1 1.3 VDDQ to VOUT (V) - 63/64 - 256M gDDR2 SDRAM Nominal Default High(18 Maximum ohms) (12 ...
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... K4N56163QG gDDR2 SDRAM Default Output Driver V–I Characteristics gDDR2 SDRAM output driver characteristics are defined for full strength default operation as selected by the EMRS1 bits A7-A9 = ‘111’. Figures 1 and 2 show the driver characteristics graphically, and tables 1 and 2 show the same data in tabular format suitable for input into simulation tools ...