RM7000A-400T PMC-Sierra Inc, RM7000A-400T Datasheet
RM7000A-400T
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RM7000A-400T Summary of contents
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... Microprocessor with On-Chip Secondary Cache Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet RM7000A™ Data Sheet Preliminary Issue No. 5: August 2002 Released 1 ...
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... U.S. Patent Numbers 5 953 748, 5 606 683, 5 760 620 Relevant patent applications and other patents may also exist. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Released 2 ...
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... Fax: +1 (604) 415-6200 Document Information: Corporate Information: Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet document@pmc-sierra.com info@pmc-sierra.com Released 3 ...
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... May 2001 1 January 2001 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Details of Change Updated pin AA2 from V Int to V Int Updated Dhrystone value from 600 to 720, page 9. ...
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... All register bit and field names described in the text, such as Interrupt Mask, are in an italic-bold typeface. · All instruction names, such as MFHI, are in san serif typeface. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Released 5 ...
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... Virtual to Physical Address Mapping........................................................................... 22 4.13 Joint TLB 23 4.14 Instruction TLB ............................................................................................................ 25 4.15 Data TLB 25 4.16 Cache Memory............................................................................................................ 25 4.17 Instruction Cache ........................................................................................................ 25 4.18 Data Cache ................................................................................................................. 26 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Released 6 ...
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... System Interface Parameters...................................................................................... 55 10.4 Boot-Time Interface Parameters ................................................................................. 55 11 Timing Diagrams ................................................................................................................... 56 11.1 Clock Timing................................................................................................................ 56 11.2 System Interface Timing.............................................................................................. 56 12 Packaging Information .......................................................................................................... 57 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet 1 ................................................................................................. 50 Released 7 ...
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... RM7000A Pinout ................................................................................................................... 58 14 Ordering Information ............................................................................................................. 60 Notes ........................................................................................................................................... 61 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Released 8 ...
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... Figure 11 Multiple Outstanding Reads ...................................................................................... 36 Figure 12 Clock Timing.............................................................................................................. 56 Figure 13 Input Timing............................................................................................................... 56 Figure 14 Output Timing............................................................................................................ 56 Figure 15 304-TBGA Drawing ................................................................................................... 57 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Released 9 ...
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... Table 22 Initialization Interface Table 3.15 V – 3.45 V)........................................................................................... 52 CC Table 2.3 V – 2.7 V).............................................................................................. 52 CC Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet ........................................................................................................... 46 .................................................................................................. 47 ................................................................................................ 47 .......................................................................................................... 48 .............................................................................................................. 48 ..................................................................................................... 49 Released 10 ...
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... Fourteen fully prioritized vectored interrupts — 10 external, 2 internal, 2 software Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet instruction allows the processor to overlap cache miss latency and ) ...
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... Fully static CMOS design with dynamic power down logic · RM5271 pin compatible, 304 pin TBGA package, 31x31 mm Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Released 12 ...
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... Block Diagram Figure 1 Block Diagram Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Released 13 ...
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... The RM7000A integrates 16 KB 4-way set associative instruction and data caches along with an integrated 256 KB 4-way set associative secondary. The primary data and secondary caches are write-back and non-blocking. An optional external tertiary cache provides high-performance capability even in applications with very large data sets ...
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... Superscalar Dispatch The RM7000A incorporates a superscalar dispatch unit that allows it to issue up to two instructions per cycle. For purposes of instruction issue, the RM7000A defines four classes of instructions: integer, load/store, branches, and floating-point. There are two logical pipelines, the function pipeline and the memory pipeline. Note however that the M pipe can execute integer as well as memory type instructions. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ ...
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... Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet M Pipe one of: integer, load/store ...
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... Integer Unit The RM7000A implements the MIPS IV™ Instruction Set Architecture. Additionally, the RM7000A includes two implementation specific instructions not found in the baseline MIPS IV ISA, but that are useful in the embedded market place. These instructions are integer multiply- accumulate ( ) and three-operand integer multiply ( ...
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... Register File The RM7000A has thirty-two general purpose registers with register location 0 (r0) hard wired to a zero value. These registers are used for scalar integer operations and address calculation. In order to service the two integer execution units, the register file has four read ports and two write ports and is fully bypassed both within and between the two execution units to minimize operation latency in the pipeline ...
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... In addition to the baseline MIPS IV integer multiply instructions, the RM7000A also implements the 3-operand multiply instruction, result go directly to the integer register file rather than the Lo register. The portion of the multiply that would have normally gone into the Hi register is discarded. For applications where ...
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... Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Repeat Rate single/double 1 ...
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... To support the non-blocking caches and enhanced interrupt handling capabilities of the RM7000A, both the data and control register spaces of CP0 are supported. In the data register space, which is accessed using the same registers as found in previous RM7000 processors. In the control space, which is accessed by the previously unused registers ...
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... These modes allow system software to provide a secure environment for user processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In user mode, the RM7000A provides a single, uniform virtual address space of 256 32-bit mode). When operating in the kernel mode, four distinct virtual address spaces, totaling 1024 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address ...
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... User virtual address space (kuseg) 0x00000000 Mapped, 2.0GB When the RM7000A is configured for 64-bit addressing, the virtual address space layout is an upward compatible extension of the 32-bit virtual address space layout. 4.13 Joint TLB For fast virtual-to-physical address translation, the RM7000A uses a large, fully associative TLB that maps virtual pages to their corresponding physical addresses ...
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... Note that both of the write-through protocols bypass both the secondary and the tertiary caches since neither of these caches support writes of less than a complete cache line. These protocols are used for both code and data on the RM7000A with data using write-back or write-through depending on the application. The write-through modes support the same efficient frame buffer handling as the RM5200 Family. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ ...
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... JTLB. The operation of the ITLB is completely transparent to the user. 4.15 Data TLB The RM7000A uses a 4-entry data TLB (DTLB) for the same reasons cited above for the ITLB. Each DTLB entry maps page. The DTLB improves performance by allowing data address translation to occur in parallel with instruction address translation. When a miss occurs on a data address translation, the DTLB is filled from the JTLB. The DTLB refill is pseudo- LRU ...
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... The RM7000A supports cache locking on a per line basis. The contents of each line of the cache can be locked by setting a bit in the Tag RAM. Locking the line prevents its contents from being overwritten by a subsequent cache miss ...
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... If the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). The store buffer allows the RM7000A to execute a store every processor cycle and to perform back-to-back stores without penalty. In the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred ...
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... The RM7000A allows entries to be stored in the primary caches that do not necessarily have a corresponding entry in the secondary; the RM7000A does not force the primaries subset of the secondary. For example, if primary cache line A is being filled and a cache line already exists in the secondary for primary cache line B at the location where primary A’ ...
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... Tertiary Cache The RM7000A has direct support for an external tertiary cache. The tertiary cache is direct mapped and block write-through with byte parity protection for data. The RM7000A tertiary cache operates identical to the secondary cache of the RM527x while supporting additional size increments to support 4 MB and 8 MB caches ...
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... RM7000 Family User Manual. The tertiary cache tag can easily be implemented with standard components such as the Motorola MCM69T618. The RM7000A cache attributes for the instruction, data, internal secondary, and optional external tertiary caches are summarized in Table 6. Table 6 Cache Attributes ...
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... Cache Locking The RM7000A allows critical code or data fragments to be locked into the primary and secondary caches. The user has complete control over the locking function. For instruction and data fragments in the primary caches, locking is accomplished by setting either or both of the cache lock enable bits and specifying the set in the CP0 ECC register, then executing either a load instruction for data Fill_I cache operation for instructions ...
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... MB/sec with a 125 MHz SysClock. Figure 8 shows a typical embedded system using the RM7000A. This example shows a system with a bank of DRAMs, an optional tertiary cache, and an interface ASIC which provides DRAM control as well as an I/O port. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ ...
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... System Address/Data Bus The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RM7000A and the rest of the system protected with an 8-bit parity check bus, SysADC[7:0]. The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies ...
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... Handshake Signals There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are driven by an external agent to indicate to the RM7000A whether it can accept a new read or write transaction. The RM7000A samples these signals before deasserting the address on read and write requests. ...
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... SysAD and SysCmd buses. If the system interface has RdRdy* asserted, then the processor tristates its drivers and releases the system interface to slave state by asserting Release*. The external agent can then begin sending data to the RM7000A. Figure 9 shows a processor block read request and the external agent read response for a system with either no tertiary cache or a transaction where the tertiary is being bypassed ...
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... RspSwap* ValidOut* ValidIn* Release* PRqst* PAck* TcMatch Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Data0 Data1 Data2 Data3 NData NData NData NEOD System Processor ...
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... WrRdy*. 4.32 External Requests The RM7000A can respond to certain requests issued by an external agent. These requests take one of two forms: Write requests and Null requests. An external agent executes a write request when it wishes to update one of the processors writable resources such as the internal interrupt register ...
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... Test/Breakpoint Registers To facilitate hardware and software debugging, the RM7000A incorporates a pair of Test/Break- point, or Watch registers, called Watch1 and Watch2. Each Watch register can be separately enabled to watch for a load address, a store address instruction address. All address comparisons are done on physical addresses. An associated register, Watch Mask, has also been added so that either or both of the Watch registers can compare against an address range rather than a specific address ...
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... Stall cycles due to pending non-blocking loads - stall start of exception [7:5] Reserved (must be zero) 8 Count in Kernel Mode 0: Disable 1: Enable Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Released 39 ...
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... When a hang occurs the interrupt ultimately triggers, thereby breaking free from the hang-up. 4.35 Interrupt Handling In order to provide better real time interrupt handling, the RM7000A provides an extended set of hardware interrupts, each of which can be separately prioritized and separately vectored. In addition to the standard six external interrupt pins, the RM7000A provides four more interrupt pins for a total of ten external interrupts ...
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... Table 13 and Table 14 above. The priority level registers are located in the coprocessor 0 control register space. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet ...
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... Standby Mode The RM7000A provides a means to reduce the amount of power consumed by the internal core when the CPU is not performing any useful operations. This state is known as Standby Mode. Executing the instruction enables interrupts and causes the processor to enter Standby WAIT Mode ...
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... Boot-Time Options The RM7000A operating modes are initialized at power-up by the boot-time mode control interface. The serial boot-time mode control interface operates at a very low frequency (SysClock divided by 256), allowing the initialization information to be kept in a low cost EPROM or system interface ASIC. ...
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... External INT5* gated to IP7 12 Enable the external tertiary cache 0: Disable 1: Enable Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Mode Description bit [17:16] System configuration identifiers - software visible in Config[21:20] ...
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... External Tertiary cache RAM type: 0: Dual-cycle deselect (DCD) 1: Single-cycle deselect (SCD) Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Mode Description bit [255:27] Reserved: Must be zero ...
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... Input RspSwap* Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Description External request Signals that the external agent is submitting an external request. Release interface Signals that the processor is releasing the system interface to slave ...
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... System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. System Command/Data Identifier Bus Parity For the RM7000A, unused on input and zero on output. Description System clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock ...
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... Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Description Tertiary Cache Data RAM Output Enable When asserted this signal causes the data RAMs to drive data onto their I/O pins ...
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... ROM When asserted, this signal indicates to the RM7000A that the V power supply has been above the recommended value for more than 100 milliseconds and will remain stable. The assertion of V initiates the reading of the boot-time mode control serial stream. ...
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... Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet 1 Limits -0.5 ...
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... CC 2. Applying a logic high state to any I/O pin before specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. Refer to the RM7000A Family Users Manual, Appendix must be connected for recommended circuit. ...
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... Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Maximum 0 0.2 V 0 ±15 µA ±15 µA Maximum 0.2 V 0.4 V 0.7 V ...
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... I/O supply power is application dependant, but typically <20 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Conditions 2 Maximum with no FPU operation Maximum worst case instruction mix Int) with worst case temperature (maximum TCase) ...
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... JTAG Clock t JTAGCKP Period Note: 1. Operation of the RM7000A is only guaranteed with the Phase Lock Loop Enabled. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Min Max ...
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... Boot-Time Interface Parameters Parameter Symbol Mode Data Setup t Mode Data Hold t Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet CPU Speed 300 MHz Min Max 5,6 (fastest) 1.0 4.5 ...
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... SysCmd, ValidIn*, ValidOut*, etc.) Figure 13 Input Timing SysClock Data Figure 14 Output Timing SysClock Data Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet t t High Low t t Fall Rise ...
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... Theta JA 13 Note: 1. All dimensions in millimeters unless otherwise indicated. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet D E1 DETA IL B TOP VIEW DETAIL A SIDE VIEW ...
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... SysAD10 L2 L20 V lnt L21 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Function Pin Function Not Connect ...
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... AC13 SS AC16 V lO AC17 SS AC20 INT5* AC21 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Function Pin Function SysAD52 M22 SysAD21 V lnt N3 SysAD12 CC SysAD51 N22 ...
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... Ordering Information RM7000A -123 Valid Combinations RM7000A-300T RM7000A-350T RM7000A-400T RM7000A-350TI Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet emperature Grade: (blank) = commercial I = Industrial Package T y pe: ...
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... Notes Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2002227, Issue 5 RM7000A™ Microprocessor with On-chip Secondary Cache Data Sheet Released 61 ...