STPCC0180BTC3 STMicroelectronics, STPCC0180BTC3 Datasheet
STPCC0180BTC3
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STPCC0180BTC3 Summary of contents
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POWERFUL X86 PROCESSOR 64-BIT BUS ARCHITECTURE 64-BIT DRAM CONTROLLER SVGA GRAPHICS CONTROLLER UMA ARCHITECTURE VIDEO SCALER DIGITAL PAL/NTSC ENCODER VIDEO INPUT PORT CRT CONTROLLER 135MHz RAMDAC 3 LINE FLICKER FILTER SCAN CONVERTER PCI MASTER / SLAVE / ARBITER CTRL ISA ...
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STPC CONSUMER X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Can access up to 4GBytes of external memory. 8KByte unified instruction and data cache with write back and write through capability. Parallel processing integral floating ...
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PCI Controller Fully compliant with PCI 2.1 specification. Integrated PCI arbitration interface masters can connect directly. External PAL allows for greater than 3 masters. Translation of PCI cycles to ISA bus. Translation of ISA master initiated cycle ...
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STPC CONSUMER 4/71 Issue 2.4 - November 8, 2001 ...
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... The STMicroelectronics x86 processor core is em- bedded with standard and application specific pe- ripheral modules on the same silicon die. The core has all the functionality of the STMicroelectronics standard x86 processor products, including the low power System Management Mode (SMM). System Management Mode (SMM) provides an ...
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GENERAL DESCRIPTION The video output pipeline incorporates a video- scaler and color space converter function and pro- visions in the CRT controller to display a video window. While repainting the screen the CRT con- troller fetches both the video as ...
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Figure 1-1 Functionnal description x86 Core Host I/F DRAM I/F ISA m/s PCI m/s PCI m/s VIP Video Color pipeline Key Chroma 2D Key SVGA CRTC HW Cursor Issue 2.4 - November 8, 2001 GENERAL DESCRIPTION ISA BUS IPC 82C206 ...
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GENERAL DESCRIPTION Figure 1-2 Typical Application ISA MUX IRQ MUX DMA.REQ DMA.ACK DMUX PCI 8/71 Super I/O RTC Flash STPC Consumer 4x 16-bit EDO DRAMs Issue 2.4 - November 8, 2001 Keyboard / Mouse Serial Ports Parallel Port Floppy 2x ...
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PIN DESCRIPTION 2.1 INTRODUCTION The STPC Consumer integrates most of the func- tionalities of the PC architecture result, many of the traditional interconnections between the host PC microprocessor and the peripheral devic- es are totally internal to ...
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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name BASIC CLOCKS AND RESETS SYSRSTI# XTALI XTALO HCLK DEV_CLK GCLK2X DCLK PCI_CLKI PCI_CLKO SYSRSTO# ISA_CLK ISA_CLK2X MEMORY INTERFACE MA[11:0] RAS#[3:0] CAS#[7:0] MWE# MD[63:0] PCI INTERFACE AD[31:0] CBE[3:0] FRAME# TRDY# IRDY# ...
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Table 2-2. Definition of Signal Pins Signal Name ISA/IDE COMBINED CONTROL IOCHRDY / DIORDY ISA CONTROL OSC14M ALE BHE# MEMR#, MEMW# SMEMR#, SMEMW# IOR#, IOW# MASTER# MCS16#, IOCS16# REF# AEN ZWS# IOCHCK# ISAOE# RTCAS GPIOCS# IDE CONTROL PIRQ SIRQ PDRQ ...
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PIN DESCRIPTION Table 2-2. Definition of Signal Pins Signal Name VIDEO INPUT VCLK VIN TV OUTPUT RED_TV, GREEN_TV, BLUE_TV VCS ODD_EVEN CVBS IREF1_TV VREF1_TV IREF2_TV VREF2_TV VSSA_TV VDDA_TV MISCELLANEOUS SPKRD SCAN_ENABLE 12/71 Dir Description I Pixel Clock I YUV Video ...
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SIGNAL DESCRIPTIONS 2.2.1 BASIC CLOCKS AND RESETS SYSRSTI System Reset/Power good. This input is low when the reset switch is depressed. Other- wise, it reflects the power supply’s power good signal. SYSRSTI is asynchronous to all clocks, and acts ...
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PIN DESCRIPTION MD[63:0] Memory Data I/O. This is the 64-bit memory data bus. If only half of a bank is populat- ed, MD63-32 is pulled high, data is on MD31-0. MD[40-0] are read by the device strap option reg- isters ...
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CVBS Analog video composite output (luminance/ chrominance). CVBS is current-driven and must be connected to analog ground over a load resis- tor (R ). Following the load resistor, a simple LOAD analog low pass filter is recommended. 2.2.5 PCI INTERFACE ...
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PIN DESCRIPTION LA[22]/SCS1# Unlatched Address (ISA)/Second- ary Chip Select (IDE) This pin has two functions, depending on whether the ISA bus is active or the IDE bus is active. When the ISA bus is active, this pins is ISA Bus ...
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ISA/IDE COMBINED CONTROL IOCHRDY/DIORDY Channel Ready (ISA)/Busy/ Ready (IDE). This is a multi-function pin. When the ISA bus is active, this pin is IOCHRDY. When the IDE bus is active, this serves as IDE signal DI- ORDY. IOCHRDY is ...
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PIN DESCRIPTION ZWS# Zero Wait State. This signal, when assert addressed device, indicates that current cy- cle can be shortened. IOCHCK# IO Channel Check. IO Channel Check is enabled by any ISA device to signal an error condition ...
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X-Bus Interface pins / IDE Data RMRTCCS# / DD[15] ROM/Real Time clock chip select. This pin is a multi-function pin. When ISAOE# is active, this signal is used as RM- RTCCS#. This signal is asserted if a ROM access ...
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PIN DESCRIPTION Table 2-3. Pinout. Pin # Pin name AF3 SYSRSTI A3 XTALI C4 XTALO G23 HCLK F25 DEV_CLK AF15 GCLK2X AF9 DCLK AD15 MA[0] AF16 MA[1] AC15 MA[2] AE17 MA[3] AD16 MA[4] AF17 MA[5] AC17 MA[6] AE18 MA[7] AD17 ...
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Pin # Pin name B21 PCI_GNT#[1] D20 PCI_GNT#[2] A5 PCI_INT[0] C6 PCI_INT[1] B4 PCI_INT[2] D5 PCI_INT[3] F2 LA[17]/DA[0] G4 LA[18]/DA[1] F3 LA[19]/DA[2] F1 LA[20]/PCS1# G2 LA[21]/PCS3# G3 LA[22]/SCS1# H2 LA[23]/SCS3# J4 SA[0] H1 SA[1] H3 SA[2] J2 SA[3] J1 SA[4] ...
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PIN DESCRIPTION Pin # Pin name D18 VDD5 A22 VDD B14 VDD C9 VDD D6 VDD D11 VDD D16 VDD D21 VDD F4 VDD F23 VDD G1 VDD K23 VDD L4 VDD L23 VDD P2 VDD T4 VDD T23 VDD ...
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STRAP OPTION This chapter defines the STPC Consumer Strap Options and their location. Memory Data Note Designation Lines MD0 1 MD16 Reserved MD17 PCI_CLKO Divisor MD18 Reserved MD19 Reserved MD20 Reserved MD21 Reserved MD22 Reserved MD23 Reserved MD24 HCLK ...
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STRAP OPTION 3.1. STRAP REGISTER DESCRIPTION 3.1.1. STRAP REGISTER 0 This register reflect the status of pins MD[7:0] respectively. They are expected to be connected on the system board to the SIMM configuration pins as follows: Strap0 7 6 MD[7] ...
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STRAP REGISTER 1 This register reflect the status of pins MD[15:8] respectively. They are expected to be connected on the system board to the SIMM configuration pins as follows: Strap1 7 6 MD[15] MD[14] MD[13] This register defaults to ...
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STRAP OPTION 3.1.3. STRAP REGISTER 2 Bits 4-0 of this register reflect the status of pins MD[20:16] respectively. Bit 5 of this register reflect the sta- tus of pin MD[23]. Bit 4 is writeable, writes to other bits in this ...
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HCLK PLL STRAP REGISTER 0 Bits 5-0 of this register reflect the status of pins MD[26:21] respectively. They are use by the chip as fol- lows: HCLK_STRAP0 7 6 Rsv MD[26] This register defaults to the values sampled on ...
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STRAP OPTION 3.1.5. 486 CLOCK PROGRAMMING (486_CLK) The bit MD[40] is used to set the clock multiplication factor of the 486 core. With the MD[40] pin pulled low the 486 will run in DX (x1) mode, while with the MD[40] ...
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ELECTRICAL SPECIFICATIONS 4.1 Introduction The electrical specifications in this chapter are val- id for the STPC Consumer. 4.2 Electrical Connections 4.2.1 Power/Ground Connections/Decoupling Due to the high frequency of operation of the STPC Consumer necessary to install ...
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ELECTRICAL SPECIFICATIONS 4.4 DC Characteristics Table 4-2. DC Characteristics Recommended Operating conditions : VDD = 3.3V Symbol Parameter V Operating Voltage DD P Supply Power DD V DAC Voltage Reference REF_DAC V Output Low Voltage OL V Output High Voltage ...
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AC Characteristics Table 4-4 through Table 4-9 list the AC character- istics including output delays, input setup require- ments, input hold requirements and output float delays. These measurements are based on the measurement points identified in rising clock edge ...
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ELECTRICAL SPECIFICATIONS Figure 4-2 CLK Timing Measurement Points (MIN) V Ref V IL (MAX) CLK One Clock Cycle LEGEND Minimum Time Minimum Time Clock ...
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Power on sequence Figure 4-3 describes the power-on sequence of the STPC, also called cold reset. There is no constraint on the rising edge of SYSRSTI#. It just needs to stay low at least 10 s after power supply ...
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ELECTRICAL SPECIFICATIONS Figure 4-3. Power-on timing diagram Power Supplies SYSRSTI# ISACLK Strap Options HCLK PCI_CLK SYSRSTO# 34/71 > 1.6 V VALID CONFIGURATION Issue 2.4 - November 8, 2001 2 ...
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RESET sequence Figure 4-4 describes the reset sequence of the STPC, also called warm reset. The constraints on the strap options and the bus activities are the same as for the cold reset. Figure 4-4. Reset timing diagram 14 ...
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ELECTRICAL SPECIFICATIONS 4.5.3 DRAM CONTROLLER AC TIMING CHARCTERISTICS Figure 4-5 Read Mode (ref table CLK tCRD RAS# CAS# MA MWE# MD Figure 4-6 Memory Early Write Mode (ref table tCMA CLK tCRP RAS# CAS# MA MWE# MD 36/71 Table 4-4) ...
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Figure 4-7 EDO Read Mode (ref table tCRAS tCMA CLK tRP tRP tCRP RAS# CAS# MA MWE# MD Figure 4-8 EDO Write Mode (ref table tCMA CLK tRP tRP tCRP RAS# CAS# MA MWE# MD Table 4-4) tCCAS tCMWE tRC ...
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ELECTRICAL SPECIFICATIONS Figure 4-9 Fast Page Mode Read (ref table tCRAS tCMA tCCAS CLK tCRP tRAH tRAD tAR tCSH tRCD RAS# tCAH tCPN tCPN tCOH CAS# MA ROW Column 1 MWE# MD Figure 4-10 Fast Page Mode Write (ref table ...
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Figure 4-11 Refresh Cycle (ref table CLK MA[11:0] tRP tRP tRPC RAS#[3:0] tCPN tCPN CAS#[7:0] Table 4-4) tCCAS tCRAS tCSR tRAS tRAS tCRS tCHR Issue 2.4 - November 8, 2001 ELECTRICAL SPECIFICATIONS tRP tRP tRPC tCSR tCPN tCPN 39/71 ...
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ELECTRICAL SPECIFICATIONS Table 4-4. AC Memory Timing Characteristics Parameter tCRAS HCLK (or GCLK2X) to RAS#[3:0] valid (see Note 3) tCCAS HCLK (or GCLK2X) to CAS#[7:0] bus valid (see Note 3) tCMA HCLK (or GCLK2X) to MA[11:0] bus valid (see Note ...
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PCI interface Table 4-5 lists the AC characteristics of the PCI in- terface. Table 4-5. PCI Bus AC Timing Name Parameter t1 PCI_CLKI to AD[31:0] valid t2 PCI_CLKI to FRAME# valid t3 PCI_CLKI to CBE#[3:0] valid t4 PCI_CLKI to ...
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ELECTRICAL SPECIFICATIONS 4.5.5 Isa interface AC Timing characteristics Table 4-12 and Table 4-6 list the AC characteris- tics of the ISA interface. Figure 4-12 ISA Cycle (ref Table ALE AEN LA [23:17] Valid Address SA [19:0] CONTROL (Note 1) IOCS16# ...
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Table 4-6. ISA Bus AC Timing Name Parameter 10c Memory access to 16-bit ISA Slave 10d Memory access to 8-bit ISA Slave 10e SA[19:0] & SBHE valid before IOR#, IOW# asserted 11 ISACLK2X to IOW# valid 11a Memory access to ...
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ELECTRICAL SPECIFICATIONS Table 4-6. ISA Bus AC Timing Name Parameter 24l Memory access to 8-bit ISA Slave Standard cycle 24 IOR#, IOW# asserted before SA[19:0] 24o I/O access to 16-bit ISA Slave Standard cycle 24r I/O access to 16-bit ISA ...
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Table 4-6. ISA Bus AC Timing Name Parameter 38l I/O access to 8-bit ISA Slave Standard Cycle 41 SA[19:0] SBHE valid to IOCHRDY negated 41a Memory access to 16-bit ISA Slave 41b Memory access to 8-bit ISA Slave 41c I/O ...
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ELECTRICAL SPECIFICATIONS Table 4-6. ISA Bus AC Timing Name Parameter 64d SMEMW# negated to write data invalid - 8-bit 64e IOW# negated to write data invalid MEMW# negated to copy data float, 8-bit ISA Slave, odd Byte 64f by ISA ...
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ELECTRICAL SPECIFICATIONS Issue 2.4 - November 8, 2001 47/71 ...
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ELECTRICAL SPECIFICATIONS 48/71 Issue 2.4 - November 8, 2001 ...
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MECHANICAL DATA 5.1. 388-PIN PACKAGE DIMENSION The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure Figure 5-1. 388-Pin PBGA Package - Top View ...
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MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols Min A 34.95 B 1.22 C 0.58 D 1.57 E 0.15 F 0.05 G 0.75 50/71 ...
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Figure 5-3. 388-pin PBGA Package - Dimensions C Solderball A Table 5-2. 388-pin PBGA Package - Dimensions Symbols Min A 0.50 B 1.12 C 0.60 D 0.52 E 0. Solderball after collapse G mm Typ ...
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MECHANICAL DATA 5.2. 388-PIN PACKAGE THERMAL DATA The 388-pin PBGA package has a Power Dissipation Capability of 4.5W. This increases to 6W when used with a Heatsink. Signal layers Figure 5-5. Thermal Dissipation Without Heatsink Board Ambient Rca Case Rjc ...
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Figure 5-6. Thermal Dissipation With Heatsink Board Ambient Rca Case Rjc Board Junction 8.5 Rjb Board Rba Ambient Rja = 9.5 °C/W Board dimensions: Junction - 10 12 layers (2 for signals, 1 GND, 1VCC) ...
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MECHANICAL DATA 54/71 Issue 2.4 - November 8, 2001 ...
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DESIGN GUIDELINES 6.1 Typical Applications The STPC Consumer is well suited for many appli- cations. Some of the possible implementations 6.1.1 Web Box A web box is an analog set top box providing inter- net browsing capability to a ...
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DESIGN GUIDELINES ing to the STPC balls, in order to reduce the jitter to the minimum and reach the optimum system stability. Figure 6-2. 14.31818 MHz stage XTALO 15pF 56/71 XTALI 15pF Issue 2.4 - November 8, 2001 XTALO XTALI ...
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PCI bus The PCI bus is always active and the following control signals must be pulled- through 2K2 resistors even if this bus is not con- nected to an external device: FRAME#, TRDY#, IRDY#, STOP#, ...
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DESIGN GUIDELINES 6.2.3 IPC Most of the IPC signals are multiplexed: Interrupt inputs, DMA Request inputs, DMA Acknowledge outputs. Figure 6-4 describes a complete imple- mentation of the IRQ[15:0] time-multiplexing. Figure 6-4. Typical IRQ multiplexing Timer 0 Keyboard Slave PIC ...
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Figure 6-5 describes a complete implementation of the external glue logic for DMA Request time- multiplexing and DMA Acknowledge demultiplex- ing. Like for the interrupt lines, this logic can be Figure 6-5. Typical DMA multiplexing and demultiplexing ISA, Refresh ISA, ...
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DESIGN GUIDELINES 6.2.4 VGA interface The STPC integrates a VGA DACs and video buff- ers. The amount of external devices is then limited to the minimum as described in the All the resistors and capacitors have close ...
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General recommendations Some STPC Interfaces run at high speed and need to be carefully routed or even shielded like: 1) Memory Interface 2) PCI bus 3) Graphics and video interfaces 4) 14 MHz oscillator stage All clock signals have ...
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DESIGN GUIDELINES 6.3.2 Thermal dissipation 6.3.2.1 Power saving Thermal dissipation of the STPC depends mainly on supply voltage. When the system does not need to work at the upper voltage limit, it may therefore be beneficial to reduce the voltage ...
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When considering thermal dissipation, one of the most important parts of the layout is the connec- tion between the ground balls and the ground lay- er. Figure 6-9. Recommended 1-wire Power/Ground Pad Layout Considering only the central matrix of 36 ...
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DESIGN GUIDELINES To avoid solder wicking over to the via pads during soldering important to have a solder mask of 4 mil around the pad (NSMD pad). This gives a di- ameter of 33 mil for a 25 ...
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As the PCB acts as a heat sink, the layout of top and ground layers must be done with care to max- imize the board surface dissipating the heat. The only limitation is the risk of losing routing chan- nels. ...
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DESIGN GUIDELINES Figure 6-14. Recommend signal wiring (top & ground layers) with corresponding heat flow GND 66/71 Power Power Issue 2.4 - November 8, 2001 Internal row STPC balls External row ...
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Issue 2.4 - November 8, 2001 DESIGN GUIDELINES 67/71 ...
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DESIGN GUIDELINES 68/71 Issue 2.4 - November 8, 2001 ...
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... ORDERING DATA 7.1 Ordering Codes STMicroelectronics Prefix Product Family PC: PC Compatible Product ID C01: Consumer Core Speed 66: 66MHz 75: 75MHz 80: 80MHz 10: 100MHz Package BT: 388 Overmoulded BGA Temperature Range C: Commercial 0 to +70°C Tcase = 0 to +100°C I: Industrial -40 to +85°C Tcase = -40 to +100°C Operating Voltage 3 : 3.3V ± ...
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... ORDERING DATA 7.2 Available Part Numbers Core Frequency Part Number STPCC0166BTC3 STPCC0180BTC3 STPCC0166BTI3 STPCC0180BTI3 70/71 CPU Mode (MHz Issue 2.4 - November 8, 2001 Tcase Range Operating Voltage (C) 0°C to +100°C 3.3V ± 0.3V -40°C to +100°C (V) ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...