ADV7322KSTZ Analog Devices, ADV7322KSTZ Datasheet
ADV7322KSTZ
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... Rev. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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ADV7322 TABLE OF CONTENTS Specifications..................................................................................... 6 Dynamic Specifications ................................................................... 7 Timing Specifications....................................................................... 8 Timing Diagrams.............................................................................. 9 Absolute Maximum Ratings.......................................................... 17 Thermal Characteristics ............................................................ 17 Pin Configuration and Function Descriptions........................... 18 Typical Performance Characteristics ........................................... 20 MPU Port Description................................................................... 24 Register ...
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Preliminary Technical Data Mode 1—Slave Option (Timing Register 0 TR0 = .............................................................................................76 Mode 1—Master Option (Timing Register 0 TR0 = 1)..........................................................................................77 Mode 2— Slave Option ...
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ADV7322 DETAILED FEATURES High definition programmable features (720p/1080i/1035i) 2× oversampling (148.5 MHz) Internal test pattern generator Color hatch, black bar, flat field/frame Fully programmable YCrCb to RGB matrix Gamma correction Programmable adaptive filter control Programmable sharpness filter control CGMS-A (720p/1080i) ...
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Preliminary Technical Data HD PIXEL Y INPUT DE- TEST INTER- CR PATTERN LEAVE CLKIN_B CB P_HSYNC TIMING P_VSYNC GENERATOR P_BLANK S_HSYNC TIMING S_VSYNC GENERATOR S_BLANK CLKIN_A CB DE- TEST INTER- CR PATTERN LEAVE SD PIXEL Y INPUT TERMINOLOGY SD: standard ...
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ADV7322 SPECIFICATIONS V = 2.375 V − 2.625 2.375 V − 2.625 (0°C to 70°C), unless otherwise noted. MIN MAX Table 2. Parameter 1 STATIC PERFORMANCE Resolution Integral Nonlinearity 2 ...
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Preliminary Technical Data DYNAMIC SPECIFICATIONS V = 2.375 V − 2.625 2.375 V − 2.625 (0°C to 70°C), unless otherwise noted. MIN MAX Table 3. Parameter PROGRESSIVE SCAN MODE Luma ...
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ADV7322 TIMING SPECIFICATIONS V = 2.375 V − 2.625 2.375 V − 2.625 (0°C to 70°C), unless otherwise noted. MIN MAX Table 4. Parameter MPU PORT 1 SCLOCK Frequency SCLOCK ...
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Preliminary Technical Data TIMING DIAGRAMS CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y7–Y0 C7–C0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure ...
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ADV7322 CLKIN_A P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y7–Y0 C7–C0 S7–S0 CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 CLKIN_B* P_HSYNC, CONTROL P_VSYNC, ...
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Preliminary Technical Data CLKIN_A P_VSYNC, CONTROL P_HSYNC, INPUTS P_BLANK Y7– CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 7. ...
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ADV7322 CLKIN_A Y7– CONTROL OUTPUTS t = CLOCK HIGH TIME CLOCK LOW TIME DATA SETUP TIME DATA HOLD TIME 12 Figure 9. PS Only 4:2:2 8-Bit Interleaved at 54 ...
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Preliminary Technical Data CLKIN_B t 9 P_HSYNC, CONTROL P_VSYNC, INPUTS P_BLANK Y7–Y0 Y0 C7–C0 Cb0 CLKIN_A t 9 S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S7–S0 Cb0 Figure 11. PS (4:2:2) and SD (8-Bit) Simultaneous Input Mode [Input Mode 011] CLKIN_B t ...
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ADV7322 CLKIN_A S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S7–S0/Y7–Y0* Cb0 CONTROL OUTPUTS *SELECTED BY ADDRESS 0x01 BIT 7 CLKIN_A S_HSYNC, CONTROL S_VSYNC, INPUTS S_BLANK S7–S0/Y7–Y0* Y0 C7–C0* Cb0 CONTROL OUTPUTS *SELECTED BY ADDRESS ...
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Preliminary Technical Data P_HSYNC P_VSYNC a P_BLANK Y7–Y0 C7–C0 a AND b AS PER RELEVANT STANDARD P_HSYNC P_VSYNC a P_BLANK Y7– CLKCYCLES FOR 525p CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 ...
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ADV7322 S_HSYNC S_VSYNC PAL = 24 CLK CYCLES NTSC = 32 CLK CYCLES S_BLANK S7–S0/Y7–Y0* *SELECTED BY ADDRESS 0x01 BIT 7 SDA SCLK Figure 17. SD Timing Input for Timing Mode ...
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 5. 1 Parameter V to AGND DGND GND_IO DD_IO Digital Input Voltage to DGND AGND to DGND DGND to GND_IO AGND to ...
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ADV7322 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS V 1 DD_IO TEST0 2 TEST1 DGND TEST2 14 TEST3 ...
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Preliminary Technical Data Table 6. Pin Function Descriptions Mnemonic Input/Output Function DGND G Digital Ground. AGND G Analog Ground. CLKIN_A I Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz). CLKIN_B I Pixel ...
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ADV7322 TYPICAL PERFORMANCE CHARACTERISTICS PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 0 –10 –20 –30 –40 –50 –60 –70 – 100 120 FREQUENCY (MHz) Figure 20. PS—UV 8× Oversampling Filter (Linear) PROG ...
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Preliminary Technical Data 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 26. Luma NTSC Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 27. Luma ...
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ADV7322 –2 –4 –6 –8 –10 – FREQUENCY (MHz) Figure 32. Luma SSAF Filter—Programmable Responses – FREQUENCY (MHz) Figure 33. Luma ...
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Preliminary Technical Data 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 38. Chroma 2.0 MHz Low-Pass Filter 0 –10 –20 –30 –40 –50 –60 – FREQUENCY (MHz) Figure 39. ...
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ADV7322 MPU PORT DESCRIPTION The ADV7322 supports a 2-wire serial (I microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the ...
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Preliminary Technical Data SDATA SCLOCK WRITE S SLAVE ADDR A(S) SEQUENCE LSB = 0 READ S SLAVE ADDR A(S) SEQUENCE S = START BIT A(S) = ACKNOWLEDGE BY SLAVE P = STOP BIT A(M) = ACKNOWLEDGE BY MASTER S 9 ...
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ADV7322 REGISTER ACCESS The MPU can write to or read from all of the registers of the ADV7322 except the subaddress registers, which are write only registers. The subaddress register determines which register the next read or write operation will ...
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Preliminary Technical Data Table 8. Registers 0x02 to 0x0F SR7– SR0 Register Bit Description 0x02 Mode Register 0 Reserved Test Pattern Black Bar Manual RGB Matrix Adjust Sync on RGB 1 RGB/YPrPb Output SD Sync HD Sync 0x03 RGB Matrix ...
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ADV7322 Table 9. Registers 0x10 to 0x11 SR7– SR0 Register Bit Description Bit 7 0x10 HD Mode HD Output Register 1 Standard Input Sync Format 0 HD/ED Input Mode ...
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Preliminary Technical Data Table 10. Register 0x12 SR7– SR0 Register Bit Description 0x12 HD Mode HD Y Delay with Respect Register to Falling Edge of HSYNC 3 HD Color Delay with Respect to Falling Edge of HSYNC HD CGMS HD ...
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ADV7322 Table 12. Register 0x15 SR7– SR0 Register Bit Description 0x15 Reserved HD Mode Register 6 HD RGB Input HD Sync on PrPb HD Color DAC Swap HD Gamma Curve A/B HD Gamma Curve Enable HD Adaptive Filter Mode HD ...
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Preliminary Technical Data Table 13. Registers 0x16 to 0x37 SR7– SR0 Register Bit Description 0x16 HD Y Level 1 0x17 Level 0x18 Level 0x19 Reserved 0x1A Reserved 0x1B Reserved 0x1C Reserved 0x1D Reserved 0x1E ...
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ADV7322 Table 14. Registers 0x38 to 0x3D SR7– SR0 Register Bit Description 0x38 HD Adaptive Filter HD Adaptive Gain 1 Filter Gain 1 Value A HD Adaptive Filter Gain 1 Value B 0x39 HD Adaptive Filter HD Adaptive Gain 2 ...
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Preliminary Technical Data Table 15. Registers 0x3E to 0x43 SR7– SR0 Register Bit Description 0x3E Reserved 0x3F Reserved 0x40 SD Mode Register 0 SD Standard SD Luma Filter SD Chroma Filter 0x41 Reserved 0x42 SD Mode Register 1 SD PrPb ...
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ADV7322 Table 16. Registers 0x44 to 0x49 SR7– SR0 Register Bit Description 0x44 SD Mode SD VSYNC-3H Register 3 SD RTC/TR/SCR SD Active Video Length SD Chroma SD Burst SD Color Bars SD DAC Swap 0x45 Reserved 0x46 SD Mode ...
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Preliminary Technical Data Table 17. Registers 0x4A to 0x58 SR7– SR0 Register Bit Description 0x4A SD Timing SD Slave/Master Register 0 Mode SD Timing Mode SD BLANK Input SD Luma Delay SD Min. Luma Value SD Timing Reset 0x4B SD ...
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ADV7322 Table 18. Registers 0x59 to 0x64 SR7– SR0 Register Bit Description 0x59 SD CGMS/WSS 0 SD CGMS Data SD CGMS CRC SD CGMS on Odd Fields SD CGMS on Even Fields SD WSS 0x5A SD CGMS/WSS 1 SD CGMS/WSS ...
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Preliminary Technical Data Table 19. Registers 0x65 to 0x7C SR7– SR0 Register Bit Description 0x65 SD DNR 2 DNR Input Select DNR Mode DNR Block Offset 0x66 SD Gamma A SD Gamma Curve A Data Points 0x67 SD Gamma A ...
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ADV7322 Table 20. Registers 0x7D to 0x91 SR7- Bit SR0 Register Description 0x7D Reserved 0x7E Reserved 0x7F Reserved 0x80 Macrovision MV Control Bits 0x81 Macrovision MV Control Bits 0x82 Macrovision MV Control Bits 0x83 Macrovision MV Control Bits 0x84 Macrovision ...
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Preliminary Technical Data INPUT CONFIGURATION Note that the ADV7322 defaults to simultaneous standard definition and progressive scan upon power-up (Address[0x01]: Input Mode = 011). STANDARD DEFINITION ONLY Address[0x01]: Input Mode = 000 The 8-bit multiplexed input data is input on ...
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ADV7322 S_VSYNC, 3 MPEG2 S_HSYNC, DECODER S_BLANK 27MHz CLKIN_A YCrCb 8 S[7:0] CrCb 8 C[7:0] INTERLACED PROGRESSIVE Y[7:0] P_VSYNC, 3 P_HSYNC, P_BLANK 27MHz CLKIN_B Figure 50. Simultaneous PS and SD Input ADV7322 S_VSYNC, 3 S_HSYNC, SDTV S_BLANK ...
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Preliminary Technical Data Table 22. Input Configurations Input Format Total Bits ITU-R BT.656 8 (4 options available) See Table Only 8 [27 MHz clock] 8 [54 MHz clock HDTV Only RGB 24 ...
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ADV7322 FEATURES OUTPUT CONFIGURATION Table 23, Table 24, and Table 25 demonstrate what output signals are assigned to the DACs when the control bits are set accordingly. Table 23. Output Configuration in SD Only Mode RGB/YUV Output SD DAC Output ...
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Preliminary Technical Data HD ASYNC TIMING MODE [Subaddress 0x10, Bits 3 and 2] For any input data that does not conform to the standards selectable in input mode, Subaddress 0x10, asynchronous timing mode can be used to interface to the ...
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ADV7322 HD TIMING RESET A timing reset is achieved by toggling the HD timing reset control bit [Subaddress 0x14, Bit 0] from this state the horizontal and vertical counters will remain reset. When this bit is ...
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Preliminary Technical Data DISPLAY 307 NO F RESET APPLIED SC DISPLAY 307 F RESET APPLIED SC LCC1 COMPOSITE ADV7183A 1 VIDEO VIDEO DECODER 14 BITS H/L TRANSITION SUBCARRIER COUNT START PHASE LOW 128 13 RTC TIME SLOT 01 NOTES 1 ...
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ADV7322 RESET SEQUENCE A reset is activated with a high-to-low transition on the RESET pin [Pin 33] according to the timing specifications. The ADV7322 will revert to the default output configuration. Figure 62 illustrates the RESET timing sequence. SD VCR ...
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Preliminary Technical Data VERTICAL BLANKING INTERVAL The ADV7322 accepts input data that contains VBI data [CGMS, WSS, VITS, and so on and HD modes. For SMPTE 293M [525p] standards, VBI data can be inserted on Lines 13 to ...
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ADV7322 SQUARE PIXEL TIMING MODE [Address 0x42, Bit 4] In square pixel mode, the following timing diagrams apply. ANALOG VIDEO INPUT PIXELS Y NTSC/PAL M SYSTEM (525 LINES/60Hz) PAL SYSTEM (625 LINES/50Hz) END OF ACTIVE VIDEO LINE HSYNC FIELD PAL ...
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Preliminary Technical Data FILTERS Table 27 shows an overview of the programmable filters available on the ADV7322. Table 27. Selectable Filters Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma ...
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ADV7322 PS/HD Sinc Filter [Subaddress 0x13, Bit 3] 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 FREQUENCY (MHz) Figure 66. HD Sinc Filter Enabled 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 ...
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Preliminary Technical Data This is reflected in the preprogrammed values for GY = 0x138B 0x93 0x3B 0x248, and RV = 0x1F0. Again if RGB matrix is enabled and another input standard is used (SD ...
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ADV7322 increments of 0.17578125°. For normal operation (zero adjustment), this register is set to 0x80. Values 0xFF and 0x00 represent the upper and lower limits (respectively) of adjustment attainable. Hue Adjust (°) = 0.17578125° ( HCR − 128) for positive ...
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Preliminary Technical Data SD Brightness Detect [Subaddress 0x7A] The ADV7322 allows monitoring of the brightness level of the incoming video data. Brightness detect is a read-only register. Double Buffering [Subaddress 0x13, Bit 7; Subaddress 0x48, Bit 2] Double buffered registers ...
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ADV7322 PROGRAMMABLE DAC GAIN CONTROL DACs A, B, and C are controlled by REG 0A. DACs D, E, and F are controlled by REG 0B. 2 The I C control registers will adjust the output signal gain up or down ...
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Preliminary Technical Data For the length 240, the gamma correction curve has to be calculated as follows γ where gamma corrected output x = linear input signal γ = gamma power factor ...
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ADV7322 HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS [Subaddresses 0x20, 0x38 to 0x3D] There are three filter modes available on the ADV7322: sharpness filter mode and two adaptive filter modes. HD Sharpness Filter Mode To enhance or attenuate the Y ...
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Preliminary Technical Data HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The following register settings were used to achieve the ...
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ADV7322 Adaptive Filter Control Application Figure 74 and Figure 75 show typical signals to be processed by the adaptive filter control block. Figure 74. Input Signal to Adaptive Filter Control Figure 75. Output Signal after Adaptive Filter Control The register ...
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Preliminary Technical Data DNR MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER NOISE SIGNAL PATH INPUT FILTER BLOCK FILTER OUTPUT Y DATA THRESHOLD? INPUT FILTER OUTPUT ! THRESHOLD MAIN SIGNAL ...
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ADV7322 1.0 FILTER D 0.8 FILTER C 0.6 0.4 FILTER B 0.2 FILTER FREQUENCY (Hz) Figure 80. DNR Input Select DNR MODE CONTROL [Address 0x65, Bit 4] This bit controls the DNR mode ...
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Preliminary Technical Data VOLTS IRE:FLT 0 VOLTS IRE:FLT 0.5 0 –2 100 L135 – Figure 82. Address 0x42, Bit 100 L135 – ...
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... VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER Output buffering on all six DACs is necessary to drive output devices, such monitors. Analog Devices produces a range of suitable op amps for this application, for example the AD8061. More information on line driver buffering circuits is given in the relevant op amps’ data sheets. ...
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Preliminary Technical Data CIRCUIT FREQUENCY RESPONSE 0 –10 –20 –30 GROUP DELAY (Sec) –40 –50 –60 –70 –80 –90 1M 10M 100M FREQUENCY (Hz) Figure 88. Filter Plot for Output Filter for PS, 8× Oversampling CIRCUIT FREQUENCY RESPONSE 0 MAGNITUDE ...
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ADV7322 For optimum performance, the analog outputs should each be source and load terminated, as shown in Figure 90. The termination resistors should be as close as possible to the ADV7322 to minimize reflections 0.1PF V ...
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Preliminary Technical Data APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM PS CGMS Data Registers [Subaddresses 0x21, 0x22, 0x23] 525p Using the vertical blanking interval 525p system, 525p CGMS conforms to the CGMS-A EIA-J CPR1204-1 (March 1998) transfer method of ...
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ADV7322 +700mV 70% r 10% 0mV –300mV 5.8Ps r 0.15Ps 6T PEAK WHITE 500mV r 25mV SYNC LEVEL 5.5Ps r 0.125Ps +100 IRE +70 IRE 0 IRE –40 IRE 11.2Ps REF BIT1 BIT2 ...
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Preliminary Technical Data +700mV 70% r 10% 0mV –300mV 4T 3.128Ps r 90ns +700mV 70% r 10% 0mV –300mV 4T 4.15Ps r 60ns REF BIT1 BIT2 ...
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ADV7322 APPENDIX 2—SD WIDE SCREEN SIGNALING [Subaddresses 0x59, 0x5A, 0x5B] The ADV7322 supports wide screen signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can be transmitted only when the device is configured in ...
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Preliminary Technical Data APPENDIX 3—SD CLOSED CAPTIONING [Subaddresses 0x51 to 0x54] The ADV7322 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of ...
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ADV7322 APPENDIX 4—TEST PATTERNS The ADV7322 can generate SD and HD test patterns CH2 200mV M 10.0Ps 30.6000Ps T Figure 98. NTSC Color Bars T 2 CH2 200mV M 10.0Ps T 30.6000Ps Figure 99. PAL Color Bars T ...
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Preliminary Technical Data T 2 CH2 200mV M 4.0Ps T 1.82872ms Figure 104. 525p Field Pattern T 2 CH2 200mV M 4.0Ps T 1.84176ms Figure 105. 625p Field Pattern T 2 CH2 EVEN Figure 106. 525p Black Bar [−35 mV, ...
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ADV7322 The register settings in Table 39 are used to generate an SD NTSC CVBS output on DAC A, S-video on DACs B and C, and YPrPb on DACs D, E, and F. Upon power-up, the subcarrier registers are programmed ...
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Preliminary Technical Data APPENDIX 5—SD TIMING MODES [Subaddress 0x4A] MODE 0 (CCIR-656)—SLAVE OPTION (TIMING REGISTER 0 TR0 = The ADV7322 is controlled by the SAV (start active video) and EAV (end active ...
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ADV7322 MODE 0 (CCIR-656)—MASTER OPTION (TIMING REGISTER 0 TR0 = The ADV7322 generates H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes ...
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Preliminary Technical Data DISPLAY 622 623 624 625 H V EVEN FIELD F DISPLAY 309 310 311 312 H V ODD FIELD F ANALOG VIDEO VERTICAL BLANK ODD FIELD VERTICAL BLANK ...
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ADV7322 MODE 1—SLAVE OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7322 accepts horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates ...
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Preliminary Technical Data MODE 1—MASTER OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7322 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the ...
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ADV7322 MODE 2— SLAVE OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7322 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates ...
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Preliminary Technical Data MODE 2—MASTER OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7322 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC ...
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ADV7322 MODE 3—MASTER/SLAVE OPTION (TIMING REGISTER 0 TR0 = this mode, the ADV7322 accepts or generates horizontal sync and odd/even field signals. ...
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Preliminary Technical Data APPENDIX 6—HD TIMING FIELD 1 1124 1125 P_VSYNC P_HSYNC FIELD 2 561 562 P_VSYNC P_HSYNC VERTICAL BLANKING INTERVAL VERTICAL BLANKING INTERVAL 563 564 565 566 567 568 569 Figure 121. ...
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ADV7322 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb OUTPUT LEVELS EIA-770.2, STANDARD FOR Y INPUT CODE 940 64 EIA-770.2, STANDARD FOR Pr/Pb 960 512 64 Figure 122. EIA 770.2 Standard Output Signals (525p/625p) EIA-770.1, STANDARD FOR Y INPUT CODE 940 64 ...
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Preliminary Technical Data RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars 700mV 525mV 300mV 700mV 300mV 700mV 300mV Figure 126. PS RGB Output Levels 700mV 525mV 300mV 0mV 700mV 300mV 0mV 700mV 300mV 0mV Figure 127. PS RGB Output Levels—RGB Sync ...
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ADV7322 YPrPb LEVELS—SMPTE/EBU N10 Pattern: 100% Color Bars 700mV Figure 130. Pb Levels—NTSC 700mV Figure 131. Pb Levels—PAL 700mV Figure 132. Pr Levels—NTSC Preliminary Technical Data 700mV Figure 133. Pr Levels—PAL 700mV 300mV Figure 134. Y Levels—NTSC 700mV 300mV Figure ...
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Preliminary Technical Data VOLTS IRE:FLT 100 0 –50 L76 MICROSECONDS PRECISION MODE OFF APL = 44.5% SYNCHRONOUS SYNC = A 525 LINE NTSC FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00V ...
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ADV7322 APPENDIX 8—VIDEO STANDARDS SMPTE 274M ANALOG WAVEFORM 4T EAV CODE F 0 INPUT PIXELS CLOCK SAMPLE NUMBER 2112 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562 SAV/EAV: LINE 563–1125 ...
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Preliminary Technical Data ACTIVE VIDEO 522 523 524 525 ACTIVE VIDEO 622 623 624 625 747 748 749 750 FIELD 1 1124 1125 FIELD 2 561 562 VERTICAL BLANK Figure 144. SMPTE ...
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... SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model 1 ADV7322KSTZ EVAL-ADV7322EB Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05135–0–9/04(PrA) 0.75 1.60 0.60 MAX 0. SEATING ...