HD6477042F28 Renesas Electronics Corporation., HD6477042F28 Datasheet
HD6477042F28
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HD6477042F28 Summary of contents
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7040, SH7041, SH7042, SH7043, SH7044, SH7045 32 ...
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Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/ SH7040 Series (CPU Core SH-2) SH7040, SH7041, SH7042, SH7043, SH7044, SH7045 Hardware Manual Group REJ09B0044-0600O ...
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Cautions ...
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Related Manual SH-1/SH-2/SH-DSP Programming Manual ...
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List of Items Revised or Added for This Version Section Page Description A/D Accuracy Mask On-chip External (5Vversion) Type Abbreviation Version ROM Bus Width Package * BF/S label 10001111dddddddd * Notes on the SH7040 Series Specifications Operating Temp Frequency Voltage ...
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Section Page Description Channel 0 is given the lowest priority. TCLKC TCLKD When BDC = output active level = high ...
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Section Page Description * * * * * * * 27.0336 Bit Rate (Bits/ Error (%) 110 3 119 0.00 150 3 87 0.00 300 2 175 0.00 600 1 87 0.00 1200 1 175 0.00 2400 1 ...
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Section Page Description 100 Rin * 2 0 Notes: Numbers are only to be noted as reference value *1 0. Rin: Input impedance PA16 (I/O)/AH (output) PA16 (I/O)/AH (output) PA15 (I/O)/CK ...
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Section Page Description 2 nF 100 0 100 0.1 F ...
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Section Page Description * *5 Make sure to set the wait times and repetitions as specified. Programming may not complete correctly if values other than the specified ones are used ...
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Section Page Description Start Set SWE bit in FLMCR1 Wait Set EBR1(2) Enable WDT Set ESU1(2) bit in FLMCR1(2) Wait 200 s Set E1(2) bit in FLMCR1(2) Wait 5 ms Clear E1(2) bit in FLMCR1(2) ...
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Section Page Description * RES MRES * IRQ7 IRQ0 BREQ IRQ7 IRQ0 RES MRES BREQ ...
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Section Page Description t TOCD t TCKS ...
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Section Page Description * Non-linearity error Offset error * Full scale error * Quantize error * – Schmitt PA2, PA5, PA6– – trigger input PA9, 0.07 voltage PE0–PE15 Analog AI — CC supply current ...
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Section Page Description Tcw1 Tcw2 Column address t CASD1 t CAC RAC t CASD1 Tcw1 Tcw2 Column address t CASD1 t CAC RAC t CASD1 CK t TOCD Output compare output ...
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Section Page IRQ2 POE2 CASH PB3 IRQ1 POE1 CASL Description On-chip flash memory * A17 Note: * Only when Pin Function Reset Class Pin Name Power-OnManual Standby Sleep Release Clock RES System I I ...
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Section Page Description Pin Function Reset Class Pin Name Power-OnManual Standby Sleep Release * * * * POE0 POE3 * * * * ADTRG * * * * * * RES Pin modes Power-Down Bus Right Standby in Bus Right ...
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Section Page Description Pin Function Reset Class Pin Name Power-On Manual Standby Sleep Release Clock RES System I I control Z * MRES WDTOVF BREQ I Z ...
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Section Page Description Pin Function Reset Class Pin Name Power-On Manual Standby Sleep Release Z * POE0–POE3 4 Port I control SCI SCK0–SCK1 I TXD0–TCD1 RXD0–RXD1 ADTRG ...
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Section Page Description Product Mask Product Code Type Version Product Mask Product Code Type Version Mark Code Package Order Model No.* Mark Code Package Order Model No ...
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CS v ...
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DREQ ...
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WDTOVF ix ...
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SH7040 Series Overview 1.1.1 SH7040 Series Features CPU: 1 ...
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IRQ0 IRQ7 ...
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RAS CAS WAIT ...
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* * * * * * ...
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* * * ...
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RES WDTOVF ...
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RES WDTOVF ADTRG IRQOUT CS3 CS2 DREQ1 DREQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 ...
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DREQ0 DREQ1 MRES DREQ0 IRQ0 DREQ1 IRQ1 CS2 CS3 IRQ2 IRQ3 CS0 CS1 WRL WRH WDTOVF RD IRQ7 ADTRG IRQ6 WAIT IRQ5 BREQ IRQ4 BACK ...
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PE14/TIOC4C/DACK0/AH 3 PE15/TIOC4D/DACK1/IRQOUT 4 Vss 5 PC0/A0 6 PC1/A1 PC2/ PC3/A3 9 PC4/A4 PC5/ PC6/A6 12 PC7/A7 PC8/ PC9/A9 15 PC10/A10 16 PC11/A11 17 PC12/A12 18 PC13/A13 19 PC14/A14 20 PC15/A15 ...
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DREQ0 DREQ1 DREQ0 IRQ0 DREQ1 IRQ1 MRES IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 DREQ0 DREQ1 CS2 CS3 CS2 CS3 IRQ2 IRQ3 CS0 CS1 WRL WRH IRQOUT ADTRG WDTOVF RD IRQ7 ADTRG IRQ6 WAIT IRQ5 BREQ IRQ4 BACK ...
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Pin No. MCU Mode IRQ0 POE0 RAS IRQ1 POE1 CASL IRQ2 POE2 CASH IRQ3 POE3 PROM Mode AH IRQOUT CE OE PGM ...
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Pin No. MCU Mode IRQ4 BACK IRQ5 BREQ IRQ6 WAIT IRQ7 ADTRG RD WDTOVF WRH WRL CS1 CS0 IRQ3 IRQ2 CS3 CS2 DREQ1 IRQI DREQ0 IRQ0 PROM Mode ...
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Pin No. MCU Mode RES DREQ0 DREQ1 PROM Mode ...
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Pin No. MCU Mode MRES PROM Mode ...
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TQFP120 Pin No. MCU Mode AH IRQOUT IRQ0 POE0 RAS IRQ1 POE1 CASL IRQ2 POE2 CASH IRQ3 POE3 PROM Mode ...
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TQFP120 Pin No. MCU Mode WDTOVF IRQ4 BACK IRQ5 BREQ IRQ6 WAIT IRQ7 ADTRG RD WRH WRL CS1 CS0 IRQ3 IRQ2 CS3 CS2 DREQ1 IRQ1 DREQ0 IRQ0 PROM Mode ...
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TQFP120 Pin No. MCU Mode RES DREQ0 DRAK0 PROM Mode ...
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TQFP120 Pin No. MCU Mode DREQ1 DRAK1 MRES PROM Mode ...
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Pin No. MCU Mode WRHH WRHL CASHH CASHL BACK PROM Mode AH IRQOUT CE ...
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Pin No. MCU Mode IRQ0 POE0 RAS IRQ1 POE1 CASL BREQ IRQ2 POE2 CASH IRQ3 POE3 IRQ4 BACK IRQ5 BREQ IRQ6 WAIT IRQ7 ADTRG RD WDTOVF ADTRG IRQOUT WRH WRL CS1 CS0 IRQ3 IRQ2 CS3 CS2 CS3 CS2 DREQ1 PROM ...
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Pin No. MCU Mode DREQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 PROM Mode ...
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Pin No. MCU Mode AH WAIT RES DREQ0 DREQ1 PROM Mode ...
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Pin No. MCU Mode DREQ0 IREQ0 DREQ1 IREQ1 MRES PROM Mode ...
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PinNo. MCU IRQ0 POE0 RAS IRQ1 POE1 CASL IRQ2 POE2 CASH IRQ3 POE3 IRQ4 BACK IRQ5 BREQ IRQ6 WAIT IRQ7 ADTRG Writer mode AH IRQOUT ...
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PinNo. MCU RD WDTOVF WRH WRL CS1 CS0 IRQ3 IRQ2 CS3 CS2 DREQ1 IRQ1 DREQ0 IRQ0 Writer mode ...
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PinNo. MCU RES DREQ0 DREQ1 Writer mode RES ...
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PinNo. MCU MRES Writer mode ...
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PinNo. MCU WRHH WRHL CASHH CASHL BACK IRQ0 POE0 RAS IRQ1 POE1 CASL BREQ IRQ2 POE2 CASH IRQ3 POE3 Writer mode AH IRQOUT ...
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PinNo. MCU IRQ4 BACK IRQ5 BREQ IRQ6 WAIT IRQ7 ADTRG RD WDTOVF ADTRG IRQOUT WRH WRL CS1 CS0 IRQ3 IRQ2 CS3 CS2 CS3 CS2 DREQ1 DREQ0 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 Writer mode ...
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PinNo. MCU AH WAIT Writer mode ...
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PinNo. MCU RES DREQ0 DREQ1 DREQ0 IRQ0 DREQ1 IRQ1 MRES Writer mode RES ...
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Classification Symbol RES MRES WDTOVF BREQ BACK I/O Name Function BREQ BACK ...
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Classification Symbol IRQ0 IRQ7 IRQOUT CS0 CS3 RD WRH WRL WAIT RAS CASH I/O Name Function ...
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Classification Symbol CASL AH WRHH WRHL CASHH CASHL I/O Name Function ...
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Classification Symbol DREQ0 DREQ1 ADTRG I/O Name Function ...
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Classification Symbol POE0 POE3 WDTOVF I/O Name Function ...
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The F-ZTAT Version Onboard Programming There are 2 modes on the F-ZTAT version: a mode that writes and overwrites programs using the special writer and a mode that writes and overwrites programs onboard the application system. When rebooting after ...
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Write control program Application program <SH7044/45> Boot program <Flash memory> Write control program area Application program Boot program area RXD1 TXD1 SCI 1 <RAM> ...
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R15, SP (hardware stack pointer) * Notes: R0 functions as an index register in the indirect indexed register addressing *1 mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination ...
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Classification Register Initial Value ...
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SH7040 Series CPU MOV.W @(disp,PC),R1 ADD R1,R0 ......... .DATA.W H'1234 Description Example of Conventional CPU ADD.W #H'1234,R0 ...
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SH7040 Series CPU BRA TRGET ADD R1,R0 SH7040 Series CPU Description CMP/GE R1,R0 BT TRGET0 BF TRGET1 ADD #1,R0 CMP/EQ #0,R0 BT TRGET Description Example of Conventional CPU ADD.W R1,R0 BRA TRGET Example of Conventional CPU CMP.W R1,R0 BGE TRGET0 ...
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Classification SH7040 Series CPU MOV MOV.W .DATA.W MOV.L .DATA.L Classification SH7040 Series CPU MOV.L MOV.B .DATA.L Classification SH7040 Series CPU MOV.W MOV.W .DATA.W Example of Conventional CPU #H'12,R0 MOV.B @(disp,PC),R0 MOV.W ................. H'1234 @(disp,PC),R0 MOV.L ................. H'12345678 @(disp,PC),R1 @R1,R0 .................. ...
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Addressing Instruction Mode Format Rn @Rn @Rn+ @–Rn Effective Addresses Calculation Equation ...
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Addressing Instruction Mode Format @(disp:4, Rn) @(R0, Rn) @(disp:8, GBR) Effective Addresses Calculation Equation ...
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Addressing Instruction Mode Format @(R0, GBR) @(disp:8, PC) Effective Addresses Calculation Equation ...
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Addressing Instruction Mode Format disp:8 disp:12 Rn #imm:8 #imm:8 #imm:8 Effective Addresses Calculation Equation ...
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Instruction Formats Source Destination Operand Operand Example NOP MOVT Rn STS MACH,Rn STC.L SR,@-Rn LDC Rm,SR LDC.L @Rm+,SR JMP @Rm BRAF Rm ...
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Instruction Formats Source Operand Destination Operand Example ADD Rm,Rn MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rm),R0 MOV.B R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn ...
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Instruction Formats Source Operand Destination Operand Example MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR) MOVA @(disp,PC),R0 BF label BRA label (label = disp + PC) MOV.L @(disp,PC),Rn AND.B #imm,@(R0,GBR) AND #imm,R0 TRAPA #imm ADD #imm,Rn ...
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Operation Classification Types Code Function No. of Instructions ...
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Operation Classification Types Code Function No. of Instructions ...
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Operation Classification Types Code Function No. of Instructions ...
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Item Format OP.Sz SRC,DEST SH-1/SH-2/SH-DSP Programming Manual Explanation ...
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Instruction MOV #imm,Rn MOV.W @(disp,PC),Rn MOV.L @(disp,PC),Rn MOV Rm,Rn MOV.B Rm,@Rn MOV.W Rm,@Rn MOV.L Rm,@Rn MOV.B @Rm,Rn MOV.W @Rm,Rn MOV.L @Rm,Rn MOV.B Rm,@–Rn MOV.W Rm,@–Rn MOV.L Rm,@–Rn MOV.B @Rm+,Rn MOV.W @Rm+,Rn MOV.L @Rm+,Rn MOV.B R0,@(disp,Rn) MOV.W R0,@(disp,Rn) MOV.L Rm,@(disp,Rn) MOV.B ...
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Instruction MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MOV.B @(R0,Rm),Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MOV.B R0,@(disp,GBR) MOV.W R0,@(disp,GBR) MOV.L R0,@(disp,GBR) MOV.B @(disp,GBR),R0 MOV.W @(disp,GBR),R0 MOV.L @(disp,GBR),R0 MOVA @(disp,PC),R0 MOVT Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Instruction Code Operation 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 0000nnnnmmmm1101 ...
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Instruction Instruction Code ADD Rm,Rn 0011nnnnmmmm1100 ADD #imm,Rn 0111nnnniiiiiiii ADDC Rm,Rn 0011nnnnmmmm1110 ADDV Rm,Rn 0011nnnnmmmm1111 CMP/EQ #imm,R0 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT Rm,Rn 0011nnnnmmmm0111 CMP/PL Rn 0100nnnn00010101 CMP/PZ Rn 0100nnnn00010001 CMP/STR ...
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Instruction Instruction Code DMULS.L Rm,Rn 0011nnnnmmmm1101 DMULU.L Rm,Rn 0011nnnnmmmm0101 DT Rn 0100nnnn00010000 EXTS.B Rm,Rn 0110nnnnmmmm1110 EXTS.W Rm,Rn 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 MUL.L Rm,Rn 0000nnnnmmmm0111 MULS.W Rm,Rn 0010nnnnmmmm1111 MULU.W Rm,Rn 0010nnnnmmmm1110 NEG ...
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Instruction Instruction Code SUB Rm,Rn 0011nnnnmmmm1000 SUBC Rm,Rn 0011nnnnmmmm1010 SUBV Rm,Rn 0011nnnnmmmm1011 Execu- tion Operation Cycles T Bit ...
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Instruction AND Rm,Rn AND #imm,R0 AND.B #imm,@(R0,GBR) NOT Rm,Rn OR Rm,Rn OR #imm,R0 OR.B #imm,@(R0,GBR) TAS.B @Rn TST Rm,Rn TST #imm,R0 TST.B #imm,@(R0,GBR) XOR Rm,Rn XOR #imm,R0 XOR.B #imm,@(R0,GBR) Instruction Code Operation 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii 0100nnnn00011011 ...
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Instruction Instruction Code ROTL Rn 0100nnnn00000100 ROTR Rn 0100nnnn00000101 ROTCL Rn 0100nnnn00100100 ROTCR Rn 0100nnnn00100101 SHAL Rn 0100nnnn00100000 SHAR Rn 0100nnnn00100001 SHLL Rn 0100nnnn00000000 SHLR Rn 0100nnnn00000001 SHLL2 Rn 0100nnnn00001000 SHLR2 Rn 0100nnnn00001001 SHLL8 Rn 0100nnnn00011000 SHLR8 Rn 0100nnnn00011001 SHLL16 ...
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Instruction Instruction Code BF label 10001011dddddddd BF/S label 10001111dddddddd BT label 10001001dddddddd BT/S label 10001101dddddddd BRA label 1010dddddddddddd BRAF Rm 0000mmmm00100011 BSR label 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP @Rm 0100mmmm00101011 JSR @Rm 0100mmmm00001011 RTS 0000000000001011 Operation Exec. T Cycles Bit ...
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Instruction Instruction Code CLRT 0000000000001000 CLRMAC 0000000000101000 LDC Rm,SR 0100mmmm00001110 LDC Rm,GBR 0100mmmm00011110 LDC Rm,VBR 0100mmmm00101110 LDC.L @Rm+,SR 0100mmmm00000111 LDC.L @Rm+,GBR 0100mmmm00010111 LDC.L @Rm+,VBR 0100mmmm00100111 LDS Rm,MACH 0100mmmm00001010 LDS Rm,MACL 0100mmmm00011010 LDS Rm,PR 0100mmmm00101010 LDS.L @Rm+,MACH 0100mmmm00000110 LDS.L @Rm+,MACL 0100mmmm00010110 ...
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Instruction Instruction Code STS.L MACH,@–Rn 0100nnnn00000010 STS.L MACL,@–Rn 0100nnnn00010010 STS.L PR,@–Rn 0100nnnn00100010 TRAPA #imm 11000011iiiiiiii Operation Exec. Cycles T Bit ...
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RES RES RES RES MRES RES RES MRES RES ...
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Transition Mode Conditions Clock CPU State On-Chip On-Chip Cache or Peripheral CPU On-Chip Modules Registers RAM I/O Port Pins Canceling ...
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Section 3 Operating Modes 3.1 Operating Modes, Types, and Selection This LSI has five operating modes and three clock modes, determined by the setting of the mode pins (MD3–MD0). Do not change the mode pin settings during LSI operation (while ...
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Table 3.2 indicates the setting method for the clock mode. Table 3.2 Clock Mode Setting MD3 MD2 3.2 Explanation of Operating Modes Table 3.3 describes the operating modes. Table 3.3 Operating Modes Mode Description Clock Mode ...
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Pin Configuration Table 3.4 describes the function of each operating mode related pin. Table 3.4 Operating Mode Pin Function Pin Name Input/Output Function ...
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Parameter Parameter Frequency (MHz Frequency (MHz ...
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IRQOUT MRES ...
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Exception Source Priority ...
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Exception Source Timing of Source Detection and Start of Processing RES RES MRES ...
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Exception Sources Vector Numbers Vector Table Address Offset ...
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Exception Sources Exception Source Vector Numbers Vector Table Address Offset Vector Table Address Calculation ...
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Conditions for Transition to Reset Status RES Type RES RES MRES MRES CPU MRES MRES Internal Status On-Chip Peripheral Module RES RES ...
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Bus Cycle Bus Type Master Bus Cycle Description MRES Address Errors ...
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Type Request Source IRQ0 IRQ7 Number of Sources ...
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Type Priority Level Comment ...
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Type Source Instruction Comment ...
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Point of Occurrence Exception Source Address Error Interrupt ...
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Types Stack Status ...
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IRQOUT ...
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IRQOUT IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ...
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IRQ0 IRQ7 IRQOUT ...
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IRQ0 IRQ7 ...
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IRQ IRQ0 IRQ7 ...
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IRQ0 IRQ7 ...
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IRQn IRQn IRQn ...
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IRQOUT IRQOUT IRQOUT IRQOUT ...
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Program execution state No Interrupt? Yes No NMI? Yes User break? Yes IRQOUT = low level * 1 Save SR to stack Yes Save PC to stack Copy accept-interrupt level IRQOUT = high level * 2 ...
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Address 4n–8 4n–4 4n Notes: *1 PC: Start address of the next instruction (return destination instruction) after the executing instruction Always be certain that multiple bits SR 32 bits SP ...
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Name Initial Abbr. R/W Value Access Address Size ...
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Bits 15 0: UBMn Description ...
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Bit 7: CP1 Bit 6: CP0 Bit 5: ID1 Bit 4: ID0 Description Description ...
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Bit 3: RW1 Bit 2: RW0 Bit 1: SZ1 Bit 0: SZ0 Description Description ...
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NMIM ...
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Name Abbreviation Bit 4 (CEDRAM) Description Initial R/W Value Address Access Size (Bits) ...
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Bit 3 (CECS3) Description Bit 2 (CECS2) Description Bit 1 (CECS1) Description Bit 0 (CECS0) Description ...
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Space Classification Address Size Bus Width ...
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CSn RD CSn RD ...
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RAS CASxx RAS CASxx ...