AM79C974KC Advanced Micro Devices, AM79C974KC Datasheet
AM79C974KC
Specifications of AM79C974KC
Related parts for AM79C974KC
AM79C974KC Summary of contents
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... SCSI-ready PCs, printers, fax This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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AMD The PCnet-SCSI is part of AMD’s PCI product family of plug-in and software compatible SCSI and Ethernet controllers. This product compatibility ensures a low cost system upgrade path and lower motherboard manufacturing costs. Ethernet Specific The PCnet-SCSI controller includes ...
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HIGH LEVEL BLOCK DIAGRAM SCSI Data SCSI Sequences, SCSI Control, SCSI Registers SCSI FIFO DMA FIFO & FIFO DMA Control 96 Bytes PCI Data/Address SCSI Control DMA Registers RCV ...
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AMD Cache SRAM Control Address CPU Data PCnet-SCSI (Am79C974) DRAM Memory Core Logic PCI Bus PC-AT ISA Bus Super I/O IDE/Floppy Ser/Par Am79C974 in a PCI System Am79C974 ...
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DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD Media Access Control Transmit and Receive Message Data Encapsulation Media Access Management Manchester Encoder/Decoder (MENDEC) External Crystal Characteristics External Clock Drive Characteristics MENDEC Transmit Path Transmitter Timing and Operation Receiver Path . . . . . . . . ...
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H_RESET, S_RESET, and STOP H_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD SCSI Power Management Features SCSI Activity Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1. Slave Configuration Read Figure 2. Slave Configuration Write Figure 3. Slave I/O Read . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD Table 1. Crystal Specifications Table 2. Clock Drive Characteristics Table 3. Bus Master Accesses Table 4. Bus Slave Accesses Table 5. EEPROM Contents Table 6. The DMA Registers Table 7. Summary of SCSI Commands Table 8. NAND Tree Configuration ...
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RELATED PRODUCTS Part No. Description Am33C93A Synchronous SCSI Controller Am386 High-Performance 32-Bit Microprocessor TM Am486 High-Performance 32-Bit Microprocessor Am53C94/96 High-Performance SCSI Controller TM Am53C974 PC SCSI Am53CF94/96 Enhanced Fast SCSI-2 Controller Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) ...
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AMD CONNECTION DIAGRAM VDDB 1 AD27 2 AD26 3 VSSB 4 AD25 5 AD24 6 C/BE3 7 VDD 8 IDSELA 9 IDSELB 10 VSS 11 AD23 12 AD22 13 VSSB 14 AD21 15 AD20 16 VDDB 17 AD19 18 AD18 ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C974 K DEVICE NUMBER/DESCRIPTION Am79C974 PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems ...
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AMD PIN DESIGNATIONS Listed by Pin Number Pin No. Pin Name Pin No. 1 VDDB 2 AD27 3 AD26 4 VSSB 5 AD25 6 AD24 7 C/BE3 8 VDD 9 IDSELA 10 IDSELB 11 VSS 12 AD23 13 AD22 14 ...
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PIN DESIGNATIONS Listed by Pin Name Pin Name Pin No. Pin Name ACK ATN 83 AD0 57 AVDD1 AD1 56 AVDD2 AD2 54 AVDD3 AD3 53 AVDD4 AD4 52 AVSS1 AD5 51 AVSS2 BSY AD6 49 BUSY AD7 48 AD8 ...
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AMD PIN DESIGNATIONS Quick Reference Pin Description Pin Name Description PCI Bus Interface AD[31:00] Address/Data Bus C/BE[3:0] Bus Command/Byte Enable CLK Bus Clock DEVSEL Device Select FRAME Cycle Frame GNTA, GNTB Bus Grant IDSELA, IDSELB Initialization Device Select INTA, INTB ...
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PIN DESIGNATIONS (continued) Quick Reference Pin Description Pin Name Description SCSI SPECIFIC SCSI Interface SD [7:0] SCSI Data SDP SCSI Data Parity MSG Message C/D Command/Data I/O Input/Output ATN Attention BSY Busy SEL Select SCSI^RST SCSI Bus Reset REQ Request ...
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AMD LOGIC SYMBOL AD [31:0] C/BE [3:0] PAR FRAME TRDY IRDY STOP DEVSEL PCI Interface IDSELA IDSELB REQA REQB GNTA GNTB CLK RST INTA INTB LOCK PERR SERR ...
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PIN DESCRIPTION PCI Bus Interface AD[31:00] Address and Data Input/Output, Active High These signals are multiplexed on the same PCI pins. During the first clock of a transaction AD[31:00] contain the physical byte address (32 bits). During the subse- quent ...
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AMD When RST is active, GNTB is an input for NAND tree testing. IDSELA Initialization Device Select Input, Active High This signal is used as a SCSI controller selection for the Am79C974 during configuration write transaction. When RST is active, ...
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The PCnet-SCSI controller monitors the PERR input during a bus master write cycle. It will assert the Data Parity Reported bit in the Status register of the Configu- ration Space when a parity error is reported by the target device. ...
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AMD LED3 LED3 Output This pin is shared with the EEDO function of the Microwire serial EEPROM interface. When functioning as LED3, the signal on this pin is programmable through BCR7. By default, LED3 is active LOW and it indicates ...
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PCnet-SCSI controller Microwire interface. At the trailing edge of the RST signal, EESK is sampled to de- termine the value of the EEDET bit in BCR19. A sam- pled HIGH value means that an EEPROM is present, and ...
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AMD SCSI Controller Pins SCSI Bus Interface Signals SCSI Bus Pins SD [7:0] SCSI Data Input/Output, Active Low, Open Drain/Active Negation, Schmitt Trigger These pins are defined as bi-directional SCSI data bus. SDP SCSI Data Parity Input/Output, Active Low, Open ...
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Miscellaneous RESERVED Reserved_DO NOT CONNECT Input This pin (#116) is reserved for internal test logic. It MUST NOT BE CONNECTED to anything for proper chip operation. It’s use is subject to change in future products. Power Supply Pins Analog Power ...
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AMD BASIC FUNCTIONS System Bus Interface Function During normal operations the Am79C974 operates as a bus master with a few slave l/O accesses for status and control functions. The Ethernet controller is initialized through a combina- tion of PCI Configuration ...
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DETAILED FUNCTIONS Bus Interface Unit (BIU) The bus interface unit is built of several state machines that run synchronously to CLK. One bus interface unit state machine handles accesses where the Am79C974 controller is the bus slave, and another handles ...
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AMD Slave Configuration Write The Slave Configuration Write command is used by the host CPU to write the configuration space in the Am79C974 controller. This allows the host CPU to CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL STOP IDSEL ...
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Slave I/O Transfers After the Am79C974 controller is configured as I/O de- vice (by setting IOEN in the PCI Command register), it starts monitoring the PCI bus for access to its internal registers. The Am79C974 controller will look for an ...
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AMD Slave I/O Write The Slave I/O Write command is used by the host CPU to write to the Am79C974’s CSRs, BCRs and EEPROM locations and SCSI and CCB registers single cy- cle, non-burst 8-bit, 16–bit, or ...
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Bus Acquisition The Am79C974 microcode (in the buffer management section) will determine when a DMA transfer should be initiated. The first step in any Am79C974 bus master transfer is to acquire ownership of the bus. This task is handled by ...
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AMD Bus Master DMA Transfers There are four primary types of DMA transfers. The Am79C974 controller uses non-burst as well as burst cycles for read and write access to the main memory. Basic Non-Burst Read Cycles All Am79C974 controller non-burst ...
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Figure 7 shows two non-burst read access within one ar- bitration cycle. The Am79C974 controller will drop FRAME between two consecutive non-burst read cy- cles. The Am79C974 controller will re-request the bus right again preempted before starting ...
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AMD Basic Non-Burst Write All Am79C974 controller non-burst write accesses are of the PCI command type Memory Write (type 7). Figure 8 shows two non-burst write access within one arbitration cycle. The Am79C974 controller will drop FRAME between two consecutive ...
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Basic Burst Read Cycles All Am79C974 controller burst read transfers are of the PCI command type Memory Read Line (type14). AD[1:0] will both be ZERO during the address phase in- dicating a linear burst order. All four byte enable signals ...
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AMD Basic Burst Write Cycles All Am79C974 controller burst write transfers are of the PCI command type Memory Write (type 7). AD[1:0] will both be ZERO during the address phase indicating a lin- ear burst order. All four byte enable ...
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Transaction Termination Termination of a PCI transaction may be initiated by either the master or the target. During termination, the master remains in control to bring all PCI transactions to an orderly and systematic conclusion regardless of what caused the ...
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AMD Disconnect Without Data Transfer Figure 12 shows a target disconnect sequence during which no data is transferred. STOP is asserted on clock 4 without TRDY being asserted at the same time. The Am79C974 controller terminates the current transfer with ...
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Target Abort Figure 13 shows a target abort sequence. The target as- serts DEVSEL for one clock. It then deasserts DEVSEL and asserts STOP on clock 4. A target can use the target abort sequence to indicate that it cannot ...
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AMD Master Initiated Termination There are three scenarios besides normal completion of a transaction where the Am79C974 controller will termi- nate the cycles it produces on the PCI bus. These are Preemption with and without FRAME assertion and Master Abort. ...
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Preemption When FRAME is Asserted The central arbiter can take GNT to the Am79C974 con- troller away if the current bus operation takes too long. This may happen, for example, when the Am79C974 controller tries to fill the whole Ethernet ...
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AMD Master Abort The Am79C974 controller will terminate its cycle with a Master Abort sequence if DEVSEL is not asserted within 4 clocks after FRAME is asserted. Master Abort is treated as a fatal error by the Am79C974 controller. For ...
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Ethernet Controller Buffer Management Unit (BMU) The buffer management unit is a micro-coded state ma- chine which implements the initialization procedure and manages the descriptors and buffers. The buffer man- agement unit operates at half the speed of the CLK ...
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AMD rently has ownership of this ring descriptor and its associated buffer. Only the owner is permitted to relin- quish ownership or to write to any field in the descriptor entry. A device that is not the current owner of ...
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When SSIZE32 = 1, software data structures are 32 bits wide. The following diagram illustrates, Figure 18, the relationship between the Initialization Base Address, the Initialization Block, the Receive and Transmit 32-Bit Base Address Pointer to Initialization Block CSR2 CSR1 ...
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AMD Polling If there is no network channel activity and there is no pre- or post-receive or pre- or post-transmit activity be- ing performed by the Am79C974 controller, then the Am79C974 controller will periodically poll the current re- ceive and ...
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Am79C974 controller will look ahead to the next trans- mit descriptor after it has performed at least one trans- mit data transfer from the first buffer. (More than one transmit data transfer may possibly take place, depend- ing upon the ...
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AMD Receive Descriptor Table Entry (RDTE) If the Am79C974 controller does not own both the cur- rent and the next Receive Descriptor Table Entry then the Am79C974 controller will continue to poll according to the polling sequence described above. If ...
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ASTRP_RCV = 1 (CSR4, bit 10), the receiver will automatically strip pad bytes from the received mes- sage by observing the value in the length field, and strip- ping excess bytes if this value is below the minimum data size ...
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AMD The status of each receive message is available in the appropriate RMD and CSR areas. FCS and Framing er- rors (FRAM) are reported, although the received frame is still passed to the host. The FRAM error will only be ...
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This transmit two part deferral algorithm is implemented as an option which can be disabled using the DXMT2PD bit in CSR3. Two part deferral after transmission is use- ful for ...
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AMD Manchester Encoder/Decoder (MENDEC) The integrated Manchester Encoder/Decoder provides the PLS (Physical Layer Signaling) functions required for a fully compliant ISO 8802-3 (IEEE/ANSI 802.3) sta- tion. The MENDEC provides the encoding function for data to be transmitted on the network ...
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The oscillator requires an external 0.01% timing refer- ence. The accuracy requirements external crystal is used are tighter because allowance for the on-board parasitics must be made to deliver a final accuracy of 0.01%. Transmission is enabled by ...
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AMD the controller portion of the Am79C974 controller sees the first ISRDCLK transition. This also strobes in the in- coming fifth bit to the MENDEC as Manchester “1”. IRXDAT may make a transition after the ISRDCLK rising edge in bit ...
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Collision Detection A MAU detects the collision condition on the network and generates a differential signal at the CI inputs. This collision signal passes through an input stage which de- tects signal levels and pulse duration. When the signal is ...
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AMD Link Test Function The link test function is implemented as specified by 10BASE-T standard. During periods of transmit pair inactivity, ’Link beat pulses’ will be periodically sent over the twisted pair medium to constantly monitor me- dium integrity. When ...
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Collision Detect Function Activity on both twisted pair signals RXD and TXD constitutes a collision, thereby causing the COL signal to be activated. (COL is used by the LED control circuits) COL will remain active until one of the two ...
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AMD Ethernet Power Savings Modes The Am79C974’s Ethernet controller supports two hard- ware power savings modes. Both are entered by driving the SLEEP pin LOW. The PCI interface section is not effected by SLEEP. In particular, access to the PCI ...
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Device ID Status Base-Class Reserved Reserved The configuration registers are accessible only by PCI configuration cycles. They can be accessed right after the Am79C974 controller is powered-on, even if the read operation of the serial EEPROM is ...
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AMD H_RESET function. EEPROM programming of the DWIO mode bit of BCR18. Automatic determination of DWIO mode due to DWORD (double-word) I/O write access to offset 10h. The Ethernet controller I/O mode setting will default to WIO after H_RESET (i.e. ...
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Accesses of non word quantities to any I/O resource are not allowed while in WIO mode, with the exception of a read to APROM locations. (A write access may cause unexpected reprogramming of the Ethernet controller control registers; a read ...
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AMD APROM Access The APROM space is a convenient place to store the value of the 48-bit IEEE station address. This space is automatically loaded from the serial EEPROM EEPROM is present. It can be overwritten by the ...
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If DWIO mode has been invoked, then the BDP has a width of 32 bits, hence, all BCR ...
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AMD Hardware Access PCnet-SCSI Controller Master Accesses The Am79C974 controller has a bus interface compat- ible with PCI specification revision 2.0. Complete descriptions of the signals involved in bus master transactions for each mode may be found in the pin ...
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Note that when I/O resource width is defined as 32 bits (DWIO mode), the upper 16 bits of the I/O resource is reserved and written as ZEROS and read as undefined, except for the APROM locations and CSR88 . The ...
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AMD EEPROM Microwire Access The Am79C974 controller contains a built-in capability for reading and writing to an external EEPROM. This built-in capability consists of a Microwire interface for di- rect connection to a Microwire compatible EEPROM, an automatic EEPROM read ...
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APROM offsets within the Am79C974 I/O resources map. Startup code in the sys- tem BIOS can perform the PCI configuration accesses, the IESRWE bit write, and the APROM writes. Direct Access to the Microwire Interface The ...
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AMD EEPROM MAP The automatic EEPROM read operation will access 18 words (i.e. 36 bytes) of the EEPROM. The format of the EEPROM WORD Byte Address Addr. Most Significant Byte 00h 01h 2nd byte of the ISO 8802-3 (lowest (IEEE/ANSI ...
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Transmit Operation The transmit operation and features of the Am79C974 controller are controlled by programmable options. The Am79C974 controller offers a136-byte Transmit FIFO to provide frame buffering for increased system latency, automatic retransmission with no FIFO reload, and automatic transmit ...
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AMD The 544 bit count is derived from the following: Minimum frame size (excluding preamble, including FCS) 64 bytes Preamble/SFD size 8 bytes FCS size 4 bytes To be classed as a minimum size frame at the receiver, the transmitted ...
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Am79C974 controller will set the CERR bit in CSR0. CERR will be asserted in 10BASE-T mode after transmit if T-MAU is in Link Fail state. CERR will never cause ...
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AMD Figure 23 shows the byte/bit ordering of the received length field for an 802.3 compatible frame format Bits Bits Preamble Sync Destination 1010....1010 10101011 Start of Frame at Time = 0 Increasing Time Figure 23. 802.3 Frame ...
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There are restrictions on loopback operation. The Am79C974 controller has only one FCS generator cir- cuit. The FCS generator can be used by the transmitter to generate the FCS to append to the frame can be used by ...
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AMD LED Default Default output Interpretation Drive Enable Output Polarity LNKST Link Status Enabled LED1 Receive Enabled LED3 Transmit Enabled For each LED register, each of the status signals is ANDed with its enable signal, and these signals are all ...
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SCSI Controller The primary function of the PCnet-SCSI controller is to transfer data between the 4 byte-wide PCI bus and 1 byte-wide SCSI bus. The controller consists of two blocks: SCSI and DMA. The SCSI block sits between the SCSI ...
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AMD wider PCI bus. All boundary conditions are handled through hardware by the DMA Engine. The DMA engine is also designed for block type (4 KByte page) transfers to support scatter-gather opera- tions. Implementation of this feature is described further ...
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Logic block via a 32-bit data bus, and the funnel logic properly reduces this stream of data to a 16-bit stream to 96-Byte DMA FIFO Figure 26. DMA FIFO to SCSI FIFO Interface SCSI DMA Programming Sequence The following section ...
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AMD Command Register (CMD) The upper 3 bytes of Command register are reserved, the remaining (LSB) byte is defined as follows: Address (B)+40h, LSB DIR INTE_D INTE_P MDL Reserved Reserved DIR: Data transfer direction bit. ...
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SMDLA 31 WMAC In this example, the contents of the WMAC register is pointing to page frame address #1. When the first entry in the MDL is read (page frame address #1), the WMAC register is incremented to point ...
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AMD When WAC (bits 11:0) again reaches the next 4K byte boundary, the next MDL entry is read into the WAC. The operation continues in this way until WMAC register reaches the last MDL entry (Page Frame Address #n in ...
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Illegal command code issued The target disconnects from the SCSI bus SCSI bus service request Successful completion of a command The Am79C974 has been reselected The Fast SCSI Block The functionality of the SCSI block is described in the following ...
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AMD When this feature is enabled, the Am79C974 will check parity on all data received from the SCSI bus. Any de- tected error will be flagged by setting bit 5 in the SCSI Status Register, and ATN will be asserted ...
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Current Transfer Count Register dec- rements to zero. Non-DMA commands do not modify the Current Trans- fer Count Register and are unaffected by the value in the Current Transfer Count Register. For non-DMA com- mands, the number ...
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AMD accept/reject the message. If non-DMA commands are used, the last byte signals the SCSI FIFO is empty. If DMA commands are used, the Current Transfer Count signals the last byte. A Reset SCSI Bus command (03h/83h) will force the ...
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Message In phase or if the Target discon- nects from the SCSI bus. This command does not utilize the Internal State Register ((B)+18h). Message Accepted Command (Command Code 12h) The Message Accepted Command is used to release ...
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AMD into the FIFO before issuing this command. This com- mand will be terminated early in the following situations: The SCSI Timeout Register times out The Target does not go to the Message Out Phase following the Selection Phase The ...
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Clear FIFO Command (Command Code 01h) The Clear FIFO Command is used to initialize the SCSI FIFO to the empty condition. The Current FIFO Register (CFISREG) reflects the empty FIFO status and the bot- tom of the FIFO is set ...
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AMD NAND Tree Testing The Am79C974 controller provides a NAND tree test mode to allow checking connectivity to the device on a printed circuit board. The NAND tree is built on all PCI bus signals (see Figure 27 and Table ...
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As shown in Figure 27, Pin 120 (RST) is the first input to the NAND tree. Pin 117 (INTA) is the second input to the NAND tree, followed by pin 118 (INTB). All other PCI bus signals follow, counterclockwise, with ...
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AMD RST must be asserted low to start a NAND tree test se- quence. Initially, all NAND tree inputs except RST should be driven high. This will result in a high output at the BUSY pin. If the NAND tree ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . Supply ...
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AMD DC CHARACTERISTICS (continued) Attachment Unit Interface Parameter Symbol Parameter Description Attachment Unit Interface (AUI) IIAXD Input Current at DI+ and DI– IIAXC Input Current at CI+ and CI– VAOD Differential Output Voltage |(DO+)–(DO–)| VAODOFF Transmit Differential ...
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DC CHARACTERISTICS (continued) SCSI Interface Parameter Symbol Parameter Description SCSI and PWDN VIH Input High Voltage All SCSI Inputs, PWDN VIL Input Low Voltage All SCSI Inputs, PWDN VIHST Input Hysteresis (Note 6) All SCSI Inputs VOH Output High Voltage ...
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AMD DC CHARACTERISTICS (continued) Capacitance, ESD, and Latch Up Parameter Symbol Parameter Description Pin Capacitance (Note 1) (VCC = 5 25∞ 1.0 MHz) CIN Input Pins CI/O I/O or Output Pins CCLK Clock Pins ...
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AC SWITCHING CHARACTERISTICS over operating range unless otherwise specified PCI Bus Interface and Board Interface Parameter Symbol Parameter Description Clock Timing CLK Frequency tCYC CLK Period tHIGH CLK High Time tLOW CLK Low Time tFALL CLK Fall Time tRISE CLK ...
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AMD AC SWITCHING CHARACTERISTICS 10BASE-T Interface Parameter Symbol Parameter Description Transmit Timing tTETD Transmit Start of Idle tTR Transmitter rise time tTF Transmitter fall time tTM Transmitter rise and fall time mismatch tPERLP Idle Signal Period tPWLP Idle Link Pulse ...
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AC SWITCHING CHARACTERISTICS Attachment Unit Interface Parameter Symbol Parameter Description AUI Port tDOTR DO+, DO– Rise Time (10% to 90%) tDOTF DO+, DO– Fall Time (10% to 90%) tDORM DO+, DO– Rise and Fall Time Mismatch tDOETD DO End of ...
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AMD AC SWITCHING CHARACTERISTICS SCSI Interface FastClk Disabled (Control Register Three (0CH) bit 3=0), See Figure 29 Parameter No. Symbol Parameter Description 1 1 tPWL Clock Pulse Width Low 2 tCP Clock Period ( Synchronization Latency 1 4 ...
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AC SWITCHING CHARACTERISTICS (continued) SCSI Interface Parameter No. Symbol Parameter Description Single Ended: Asynchronous Initiator Transmit, See Figure 30 Data to ACK 7 tS REQ 8 tPD REQ 9 tPD REQ 10 tPD Single Ended: Asynchronous Initiator Receive, See Figure ...
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AMD KEY TO SWITCHING WAVEFORMS AC SWITCHING TEST CIRCUITS Sense Point 100 WAVEFORM INPUTS Must be Steady May Change from May Change from ...
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AC SWITCHING TEST CIRCUITS DO+ DO– TXD+ TXD– Includes test jig capacitance TXP+ TXP– Includes test jig capacitance 52.3 Test Point 154 100 18681A-38 ...
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AMD AC SWITCHING WAVEFORMS System Bus Interface CLK CLK AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL, IDSEL GNT 102 HIGH 2.4V 2 LOW 1.5 ...
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AC SWITCHING WAVEFORMS System Bus Interface CLK AD[31:00] C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL, PERR, SERR REQ CLK AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL P R ...
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AMD AC SWITCHING WAVEFORMS 10BASE-T Interface TXD+ TXP+ TXD– TXP– t XMTON XMT (Note 1) Note: 1. Internal signal and is shown for clarification only. t PWPLP TXD+ TXP+ TXD– TXP– t PWLP 104 ...
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SWITCHING WAVEFORMS 10BASE-T Interface RXD RXD Receive Thresholds (LRT=0) Receive Thresholds (LRT=1) Am79C974 AMD V TSQ+ V THS+ V THS– V TSQ– tmau_RCV_LRT_HI 18681A-47 V LTSQ+ V LTHS+ V ...
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AMD AC SWITCHING WAVEFORMS Attachment Unit Interface XTAL1 t XI ISTDCLK (Note 1) ITXEN (Note 1) 1 ITXDAT+ (Note 1) DO+ DO– DO Note: 1. Internal signal and is shown for clarification only. XTAL1 ISTDCLK (Note 1) ITXEN (Note 1) ...
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SWITCHING WAVEFORMS Attachment Unit Interface XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ (Note 1) DO+ DO– Bit (n–2) Note: 1. Internal signal and is shown for clarification only. Transmit Timing – End of Frame (Last ...
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AMD AC SWITCHING WAVEFORMS Attachment Unit Interface CI+/– V ASQ t PWOCI DO+/– 108 PWKCI Collision Timing t DOETD 40 mV 100 mV max. 80 Bit Times Port ...
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AC SWITCHING TEST WAVEFORMS SCSI Interface 2.3 V 0.8 V SCSI CLK SD [7:0] SDP ACK REQ Figure 30. Asynchronous Initiator Transmit All Inputs True Data Outputs SD [7:0], ...
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AMD AC SWITCHING TEST WAVEFORMS SCSI Interface SD [7:0] SDP ACK REQ SD [7:0] SDP REQ ACK SD [7:0] SDP REQ ACK 110 Figure 31. Asynchronous Initiator ...
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... Copyright 1994 Advanced Micro Devices, Inc. All rights reserved. AMD and the AMD logo are registered trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies ...
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APPENDIX A Register Summary Ethernet PCI Configuration Registers Note read only read/write undefined value Offset Name 00h Vendor ID 02h Device ID 04h Command 06h Status 08h Revision ID 09h Programming IF 0Ah Sub-Class ...
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Ethernet Controller Control and Status Registers Note undefined value Running register Setup register Test register Default Value RAP Addr Symbol H_RESET 00 CSR0 uuuu 0004 01 CSR1 uuuu uuuu 02 CSR2 uuuu ...
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AMD Control and Status Registers (continued) Default Value RAP Addr Symbol H_RESET 22 CSR22 uuuu uuuu 23 CSR23 uuuu uuuu 24 CSR24 uuuu uuuu 25 CSR25 uuuu uuuu 26 CSR26 uuuu uuuu 27 CSR27 uuuu uuuu 28 CSR28 uuuu uuuu ...
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Control and Status Registers (continued) Default Value RAP Addr Symbol H_RESET 65 CSR65 uuuu uuuu 66 CSR66 uuuu uuuu 67 CSR67 uuuu uuuu 68 CSR68 uuuu uuuu 69 CSR69 uuuu uuuu 70 CSR70 uuuu uuuu 71 CSR71 uuuu uuuu 72 ...
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AMD Control and Status Registers (continued) Default Value RAP Addr Symbol H_RESET 108 CSR108 uuuu uuuu 109 CSR109 uuuu uuuu 110 CSR110 uuuu uuuu 111 CSR111 uuuu uuuu 112 CSR112 uuuu 0000 113 CSR113 uuuu uuuu 114 CSR114 uuuu 0000 ...
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SCSI Controller SCSI Register Map Register Acronym Address (Hex.) CTCREG (B)+00 STCREG (B)+00 CTCREG (B)+04 STCREG (B)+04 FFREG (B)+08 CMDREG (B)+0C STATREG (B)+10 SDIDREG (B)+10 INSTREG (B)+14 STIMREG (B)+14 ISREG (B)+18 STPREG (B)+18 CFISREG (B)+1C SOFREG1 (B)+1C CNTLREG1 (B)+20 CLKFREG ...
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APPENDIX B PCnet-SCSI Compatible Media Interface Modules PCnet-SCSI COMPATIBLE 10BASE-T Filters and Transformers Manufacturer Part # Bel Fuse A556-2006-DE Bel Fuse 0556-2006-00 Bel Fuse 0556-2006-01 Bel Fuse 0556-6392-00 Halo Electronics FD02-101G Halo Electronics FD12-101G Halo Electronics FD22-101G PCA Electronics EPA1990A ...
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PCnet-SCSI COMPATIBLE AUI Isolation Transformers Manufacturer Bel Fuse Halo Electronics Halo Electronics PCA Electronics Pulse Engineering TDK Valor Electronics MANUFACTURER CONTACT INFORMATION Contact the following companies for further information on their products: Bel Fuse Phone: (317) 831-4226 FAX: (317) 831-4547 ...
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APPENDIX C Recommendation for Power and Ground Decoupling The PCnet-SCSI controller is an integrated, combina- tion Ethernet and Fast SCSI controller, which contains both digital and analog circuitry. The analog circuitry contains a high speed Phase-Locked Loop (PLL) and Voltage ...
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To determine the value for the resistor and capacitor, the formula is Where ohms and microfarads. Some pos- sible combinations are given below. To minimize the voltage drop across the ...
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APPENDIX D Alternative Method for Initialization of Ethernet Controller The Ethernet portion of the PCnet-SCSI controller may be initialized by performing I/O writes only. That is, data can be written directly to the appropriate control and status registers (CSR) instead ...
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APPENDIX E SCSI System Considerations INTRODUCTION This appendix covers motherboard design considera- tions which use the Am79C974. It discusses SCSI com- ponent placement, signal routing, PCI interface recommendations, noise considerations and termina- tion schemes. SIGNAL ROUTING AND SCSI PLACEMENT The ...
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AMD High-Density SCSI-2 Connectors External Peripheral External SCSI-2 Bus Cable High-Density SCSI-2 Termination The Motherboard The following two layouts may be used as a guideline for the design of motherboards which incorporate the Am79C974. For both layouts, the SCSI connectors ...
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External SCSI-2 Bus Cable Bracketed card joining ribbon cable with high-density High-Density SCSI-2 cable SCSI-2 Connector External Peripheral High-Density SCSI-2 Termination Figure E-3. Motherboard Layout — Approach #1 Layout #2 This approach uses a “pizza-box” type of motherboard, which has ...
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AMD Keyboard Connector High-Density To SCSI CLK1 SCSI-2 and CLK2 Connectors 25 External Peripheral External SCSI Bus Cable Mounted High-Density High-Density SCSI-2 SCSI-2 Connector Termination Figure E-4. Motherboard Layout — Approach #2 Motherboard designs which place an internal and exter- ...
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From an EMI standpoint, SCSI-2 high-density ca- bles should be used instead of a SCSI-1 cables. Unlike the SCSI-1 flat ribbon cable, the SCSI-2 cable is electrically more substantial shielded and signal wires are strategically placed for better ...
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...
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Decoupling methods which are NOT recommended include: connecting a capacitor only between the VDD and VSS planes so that it sits on the component side of the board. This doesn’t allow the capacitor to re- duce noise directly at the ...
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AMD Termination There are three general termination schemes that apply to motherboard or host adapter setups when using regu- lated terminators. Each scheme recognizes that the SCSI bus must be terminated on both ends. Therefore, as more components and peripherals ...
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APPENDIX F Designing a Single Motherboard for AMD PCI Family Three devices in the AMD PCI family, the Am53C974, the Am79C970, and the Am79C794, were designed with very similar pin assignments so that a single mothe- rboard design could be ...
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AMD them to multiplex logic that can map these outputs to in- terrupt controller inputs by means of software. REQ and GNT (pins 123, 124, 126, and 127) The Am53C974 uses pins 127 and 124 (REQ and GNT) for bus ...
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Crystal SCSI OSC. BUS Arbiter ADx ADy IRQ1 IRQ2 . MUX . . IRQ15 MUX Control Figure F-1. PCI Family Connections XTAL2 97 XTAL1/SCSICLK2 60 SCSICLK1 127 REQA ...
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... AMD, the AMD logo, and Am386 are registered trademarks of Advanced Micro Devices, Inc. GLITCH EATER, PCnet HIMIB, MACE, ILACC, IMR+, and Am486 are trademarks of Advanced Micro Devices, Inc. SCSI Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...
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AMENDMENT Am79C974 TM PCnet -SCSI Combination Ethernet and SCSI Controller for PCI Systems This amendment corrects a few minor inaccuracies and adds or clarifies a few sections. Minor corrections should be made on the existing data sheets. However, for ease ...
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AMD Page 19 (Reprinted as page 9 of this amendment) PIN DESCRIPTION, GNTA Add after the second paragraph: The Am79C974 supports bus parking. When the PCI bus is idle and the system arbiter asserts GNTA without an active REQA from ...
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Page 44 Change SPRINTEN to LAPPEN in lines 12 and 13. Page 54 Line 17, change 100% to 10%. Page 59 Line 12 should read, “When the Am79C974 controller samples its IDSELA or IDSELB input ...” (The original ommitted “IDSELA”). ...
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AMD Page 94 In the DC Characteristics table, delete row 5, VSOL1. Change the parameter symbol for row 6 from VSOL2 to VOL. Add SD[7:0] and SDP to the parameter description for row 6. Page 95 In the DC Characteristics ...
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CONNECTION DIAGRAM VDDB 1 AD27 2 AD26 3 VSSB 4 AD25 5 AD24 6 C/BE3 7 VDD 8 IDSELA 9 IDSELB 10 VSS 11 AD23 12 AD22 13 VSSB 14 AD21 15 AD20 16 VDDB 17 AD19 18 AD18 19 ...
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AMD PIN DESIGNATIONS Listed by Pin Number Pin No. Pin Name Pin No. 1 VDDB 2 AD27 3 AD26 4 VSSB 5 AD25 6 AD24 7 C/BE3 8 VDD 9 IDSELA 10 IDSELB 11 VSS 12 AD23 13 AD22 14 ...
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PIN DESIGNATIONS Listed by Pin Name Pin Name Pin No. Pin Name ACK ATN 83 AD0 57 AVDD1 AD1 56 AVDD2 AD2 54 AVDD3 AD3 53 AVDD4 AD4 52 AVSS1 AD5 51 AVSS2 BSY AD6 49 BUSY AD7 48 AD8 ...
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AMD PIN DESIGNATIONS (continued) Quick Reference Pin Description Pin Name Description SCSI SPECIFIC SCSI Interface SD [7:0] SCSI Data SDP SCSI Data Parity MSG Message C/D Command/Data I/O Input/Output ATN Attention BSY Busy SEL Select SCSI^RST SCSI Bus Reset REQ ...
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PIN DESCRIPTION PCI Bus Interface AD[31:00] Address and Data Input/Output, Active High These signals are multiplexed on the same PCI pins. During the first clock of a transaction AD[31:00] contain the physical byte address (32 bits). During the subse- quent ...
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AMD Bus Master DMA Transfers There are four primary types of DMA transfers. The Am79C974 controller uses non-burst as well as burst cycles for read and write access to the main memory. Basic Non-Burst Read Cycles All Am79C974 controller non-burst ...
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Target Abort Figure 13 shows a target abort sequence. The target as- serts DEVSEL for one clock. It then deasserts DEVSEL and asserts STOP on clock 4. A target can use the target abort sequence to indicate that it cannot ...
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AMD Master Abort The Am79C974 controller will terminate its cycle with a Master Abort sequence if DEVSEL is not asserted within 4 clocks after FRAME is asserted. Master Abort is treated as a fatal error by the Am79C974 controller. For ...
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Since the PCI bus is 4 bytes wide and the SCSI bus is only 1 byte wide, funneling logic is included in this en- gine to handle byte alignment and to ensure that data is properly transferred between the SCSI ...
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AMD have yet to be transferred from the SCSI peripheral de- vice and must start a new transfer operation to get the rest of the data. (CTCREG consists of three bytes lo- cated at ((B)+00h, (B)+04h, and (B)+38h.) Funneling Logic ...
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DMA Registers The following is a summary of the DMA register set or the DMA Channel Context Block (DMA CCB). These registers control the specifics for DMA operations such as transfer length and scatter-gather options. The three read-only working counter ...
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AMD DMA Scatter-Gather Mechanism The Am79C974 contains a scatter-gather translation mechanism which facilitates faster data transfers. This feature uses a Memory Descriptor List (a list of contigu- ous physical memory addresses) which is stored in sys- tem memory. Use of ...
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In this example, the contents of the WMAC register is pointing to page frame address #1. When the first entry in the MDL in read (page frame address #1), the WMAC register is incremented to point to the next page ...
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AMD When WAC (bits 11:0) again reaches the next 4K byte boundary, the next MDL entry is read into the WAC. The operation continues in this way until WMAC register reaches the last MDL entry (Page Frame Address #n in ...
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C1 – C9 are decoupling capacitors. Figure E-5. Decoupling Capacitor Placement Am79C974 AMD 18681A/1-67 19 ...