S82503 Intel Corporation, S82503 Datasheet
S82503
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S82503 Summary of contents
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... The 82503 includes on-chip AUI and TPE drivers and receivers it offers designers a cost-effective integrated solution for interfacing LAN control- lers to the wire medium CHMOS is a patented process of Intel Corporation Ethernet is a registered trademark of Xerox Corporation LANCE is a registered trademark of Advanced Micro Devices ...
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Dual Serial Transceiver (DST) CONTENTS 1 0 82503 PRODUCT FEATURES 2 0 PIN DEFINITION 2 1 Power Pins 2 2 Clock Pins 2 3 AUI Pins 2 4 TPE Pins 2 5 Controller Interface Pins 2 6 Mode Pins ...
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Figure 1 Application Block Diagram 1 0 82503 PRODUCT FEATURES The 82503 incorporates all the active circuitry re- quired to interface Ethernet controllers to 10BASE-T networks or the attachment unit interface (AUI) It supports a direct no-glue interface to Intel’s ...
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Figure 2 82503 Functional Block Diagram 4 290421 – 2 ...
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PIN DEFINITION Figure 3 44-Lead PLCC Pin Configuration Figure 4 44-Lead QFP Pin Configuration 82503 290421 –3 290421 –44 5 ...
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Power Pins PLCC QFP Symbol Pin Pin ( ( ( CCA ( SSA NOTE 1 V and ...
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TPE Pins PLCC QFP Symbol Type Pin Pin TDH TDH TDL TDL Controller Interface Pins PLCC ...
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Mode Pins PLCC QFP Symbol Type Pin Pin TPE AUI APORT APOL XSQ LID CS0 CS1 LPBK 11 ...
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LED Pins PLCC QFP Symbol Type Pin Pin TxLED RxLED COLED LILED POLED NOTE 1 The LED outputs have a ...
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ARCHITECTURE 3 1 Clock Generation A 20 MHz parallel resonant crystal is used to control the clock generation oscillator which provides the basic 20 MHz clock source An internal divide-by- two counter generates the 10 MHz ...
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Receive Blocks MANCHESTER DECODER AND CLOCK RECOVERY The 82503 performs Manchester decoding and tim- ing recovery of the incoming data in AUI and TPE modes The Manchester-encoded data stream is decoded to separate the Receive ...
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Figure 6 Manchester Decoder and Clock Recovery AUI RECEIVE AND COLLISION BUFFERS The AUI receive and collision inputs are driven through isolation transformers to provide high volt- age protection and DC common mode voltage rejec- tion ...
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TPE extended squelch mode is enabled by present- ing a high-impedance ( 100 the APOL XSQ l pin This can be done by floating the APOL XSQ pin tying APOL XSQ low through a 100 K driving ...
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The transmit to receive loopback function is disabled when the jabber function or link integrity function is inhibiting transmission 3 8 SQE Test Function The 82503 supports the SQE test function when in TPE mode or in Diagnostic Loopback ...
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Figure 7 Polarity Fault State Diagram polarity error due to crossed wires If Pin 4 of the 82503 is high and the TPE receive pins are re- versed the 82503 will correct the error by reversing the signals internally and ...
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Table 2 Controller Interface Selection Intel 82503 Controller Pin 825XX (1) CS0 0 CS1 0 Pin Pin Sense TxC TxC Low TxD TxD High RTS RTS Low RxC RxC Low RxD RxD High CRS CRS Low CDT CDT Low ...
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Table 3 Test and Low Power Mode Selection RESET TEST JABD NOTE 1 A standard LED connection to these pins is sufficient to pull them to a logic 1 The port on which the ...
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Figure 8 Application Example Schematic 18 290421 –7 ...
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Make power supply and ground traces as thick as possible This will reduce high-frequency cross cou- pling caused by the inductance of thin traces Connect logic and chassis ground together Separate and decouple all of the analog and digital power ...
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ELECTRICAL SPECIFICATIONS AND TIMINGS ABSOLUTE MAXIMUM RATINGS Case Temperature Under Bias Storage Temperature All Output and Supply Voltages b All Input Voltages CHARACTERISTICS ( Symbol Parameter ...
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DC CHARACTERISTICS ( Symbol Parameter I (AUI) AUI Output Short Circuit Current OSC V (AUI) Output Differential Undershoot U (11) V (AUI) Differential Idle Voltage ODI (12) I (HOT) Power Supply Current CC I Power Supply Current CC ...
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AC TIMING CHARACTERISTICS (Continued) Figure 13 Voltage Levels for TDH TDL TDH and TDL AC MEASUREMENT CONDITIONS The AC MOS TTL and differential ...
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Controller Interface Timings (Intel Mode) TRANSMIT TIMINGS (Intel) Symbol Parameter t TxC Cycle Time 10 t TxC High Low Time 11 t TxC Rise Fall Time 12 t TxD and RTS Rise Fall Time 13 t TxD Setup Time to ...
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RECEIVE TIMING (Intel) Symbol Parameter t RxC Cycle Time 20 t RxC High Time 21 t RxC Low Time 22 t RxC Rise Fall Time 23 t RxC Delay from CRS 24 t RxD Rise Fall Time 25 t ...
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Controller Interface Timings (National Mode) TRANSMIT TIMINGS (National) Symbol Parameter (16) t TXC Cycle Time 30 t TXC High Low Time 31 t TXC Rise Fall Time at 20 TXD Setup Time to TXC 33 t ...
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RECEIVE TIMINGS (National) Symbol Parameter t RxC Cycle Time 40 t RxC High Low Time 41 t RxC Rise Fall Time at 20 RXD Rise Fall Time at 20 RXD Setup ...
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Controller Interface Timing (AMD Mode) (18) TRANSMIT TIMINGS (AMD) Symbol Parameter t TCLK Cycle Time 50 t TCLK High Time ( 51 t TCLK Low Time ( 52 t TCLK Rise Fall Time ( Setup Time to ...
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RECEIVE TIMINGS (AMD) Symbol Parameter t RCLK Cycle Time 60 t RCLK High Time ( 61 t RCLK Low Time ( 8V RCLK Rise Fall Time ( Rise Fall ...
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Controller Interface Timings (Fujitsu Mode) TRANSMIT TIMINGS (Fujitsu) Symbol Parameter t TCKN Cycle Time 70 t TCKN High Low Time 71 t TCKN Rise Fall Time at 20 TXD Setup Time to TCKN 73 t TXD ...
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RECEIVE TIMINGS (Fujitsu) Symbol Parameter t RCKN Cycle Time 80 t RCKN High Low Time 81 t RCKN Rise Fall Time at 20 RXD Setup Time from RCKN 83 t RXD Hold Time from RCKN ...
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TPE Timings TPE TRANSMIT TIMINGS Symbol t TxD to TD Bit Loss at Start of Packet 90 t TxD to TD Steady State Propagation Delay 91 t TxD to TD Startup Delay 92 t TDH and TDL Pairs Edge Skew ...
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Figure 28 TPE Transmit Timings (Link Test Pulse) TPE RECEIVE TIMINGS Symbol Parameter RxD Bit Loss at Start of Packet 105 RxD Invalid Bits Allowed at Start of Packet 106 ...
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Figure 30 TPE Receive Timings (End of Frame) TPE COLLISION TIMINGS Symbol Parameter t Onset of Collision (RD Pair and RTS Active) to CDT Assert 115 t End of Collision (RD Pair or RTS Inactive) to CDT Deassert 116 t ...
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Figure 32 TPE Collision Timings (End of Collision) TPE LINK INTEGRITY TIMINGS Symbol Parameter t Last RD Activity to Link Fault (Link Loss Timer) 120 t Minimum Received Linkbeat Separation 121 t Maximum Received Linkbeat Separation 122 NOTES 20 ...
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AUI Timings AUI TRANSMIT TIMINGS Symbol Parameter t TxD to TRMT Pair Steady State Propagation Delay 125 t TRMT Pair Rise Fall Times 126 t Bit Cell Center to Bit Cell Center of TRMT Pair 127 t Bit Cell Center ...
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AUI COLLISION TIMINGS Symbol Parameter t CLSN Pair Cycle Time 145 t CLSN Pair Rise Fall Times 146 t CLSN Pair Return to Zero from Last Positive Transition 147 t CLSN Pair High Low Times 148 t CDT Assertion ...
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LOOPBACK TIMINGS Symbol Parameter t TxD to RxD Bit Loss at Start of Packet 155 t TxD to RxD Steady State Propagation Delay 156 t TxD to RxD Startup Delay 157 t SQE Test Wait Time 158 t SQE Test ...
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JABBER TIMINGS Symbol Parameter t Maximum Length Transmission before Jabber Fault (TPE) 165 t Maximum Length Transmission before Jabber Fault (AUI) 166 t Minimum Idle Time to Clear Jabber Function 167 LED TIMINGS Symbol Parameter t TxLED RxLED COLED ...
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MODE TIMINGS Symbol Parameter t Mode Pins Setup to RTS 175 t Mode Pins Hold from RTS 176 t Mode Pins Setup to RD Active 177 t Mode Pins Hold from RD Active 178 NOTES 23 Guarantees Proper ...
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RESET TEST AND LOW POWER MODE TIMINGS Symbol Parameter t TEST and JABD Setup Time to RESET 180 t RESET Pulse Width 181 t Low Power Mode Deactivation from TEST and JABD 182 Figure 42 Reset Timings (Test Mode) ...
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PACKAGE DIMENSIONS PLASTIC LEADED CHIP CARRIER Figure 45 Principle Dimensions and Data Figure 46 Molded Details 82503 290421 –45 290421 –46 41 ...
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Figure 48 Standard Package Bottom View (Tooling Option 1) 42 Figure 47 Terminal Details 290421 –47 290421 –48 ...
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Figure 49 Standard Package Bottom View (Tooling Option II) Figure 50 Detail J Terminal Detail 82503 290421 –49 290421 –50 43 ...
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Figure 51 Detail L Terminal Details NOTES The above diagrams use a 20-lead PLCC package to show symbols for package dimensions The table below indicates dimensions in mm that are specific to the 44-lead PLCC package 1 All dimensions ...
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QUAD FLATPACK PACKAGE Figure 52 44-Lead Quad Flatpack Package Symbol Description A Package Height A1 Stand Off B Lead Width C Lead Thickness D Package Body 1 E Package Body 1 e Lead Pitch 1 D Terminal Dimension E ...