ADV473KP110 Analog Devices, ADV473KP110 Datasheet
ADV473KP110
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ADV473KP110 Summary of contents
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... System/2 and VGA are trademarks of International Business Machines Corp. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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ADV473–SPECIFICATIONS Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error Coding DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance DIGITAL OUTPUTS ...
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TIMING CHARACTERISTICS 135 MHz 110 MHz Parameter Version Version fmax 135 110 ...
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... Analog output short circuit to any power supply or common can indefinite duration. ORDERING GUIDE Temperature No. of Package Model Speed Range ADV473KP135 135 MHz +70 C ADV473KP110 110 MHz +70 C ADV473KP80 80 MHz +70 C ADV473KP66 66 MHz +70 C NOTE * All devices are packaged in a 68-pin plastic leaded (J-lead) chip carrier. ...
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PIN FUNCTION DESCRIPTION BLANK Composite Blank Control Input (TTL Compatible). A logic zero drives the analog outputs to the blanking level latched on the rising edge of CLOCK. When BLANK is a logical zero, the pixel and overlay ...
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ADV473 TERMINOLOGY BLANKING LEVEL The level separating the SYNC portion from the video portion of the waveform. Usually referred to as the front porch or back porch IRE units the level which will shut off the ...
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ADDRa,b (Counts Modulo 3) ADDR0-7 (Counts Binary) Overlay Color Writes The MPU writes to the address register (selecting OVERLAY REGISTER write mode, RS2 = 1, RS1 = 0 and RS0 = 0) with the address of the overlay register to ...
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ADV473 Command Register (CR) The ADV473 has an internal command register (CR). This reg- ister is 8 bits wide, CR0–CR7 and is directly mapped to the MPU data bus on the part, D0–D7. The command register can be written to ...
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VIDEO MODES 24-Bit True-Color Mode Twenty-four bits of RGB color information may be input into the ADV473 every clock cycle. The 24 bits of pixel information are input via the R0–R7, G0–G7, and B0–B7 inputs. R0–R7 ad- dress the red ...
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ADV473 MA V 26.67 1.000 92.5 IRE 9.05 0.340 7.5 IRE 7.62 0.286 40 IRE 0.00 0.000 NOTE: 75 DOUBLY TERMINATED LOAD, SETUP = 7.5 IRE, V RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS. Figure 5. Composite Video Output ...
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PC BOARD LAYOUT CONSIDERATIONS The layout should be optimized for lowest noise on the ADV473 power and ground lines by shielding the digital inputs and pro- viding good decoupling. The lead length between groups of V and GND pins should ...
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... GND should be as close as pos- sible to the ADV473 to minimize reflections. For more information on circuit board design and layout, see application note entitled “Design and Layout of a Video Graph- ics System for Reduced EMI” available from Analog Devices, Publication No. E1309-15-10/89. POWER SUPPLY DECOUPLING 0.1 F ...