ADSP-21062L Analog Devices, ADSP-21062L Datasheet
ADSP-21062L
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ADSP-21062L Summary of contents
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC SUMMARY High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a ...
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... MBps transfer rate over parallel bus 240 MBps transfer rate over link ports SERIAL PORTS Two 40 Mbps synchronous serial ports with companding hardware Independent transmit and receive functions ADSP-21060L ADSP-21062L 4M bits 2M bits 3 MHz 33 MHz 40 MHz 40 MHz ...
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... Corrected model package descriptions. See Ordering Guide.................................................. ADSP-21060/ADSP-21062 Specifications ..................... 15 Operating Conditions (5 V) ................................... 15 Electrical Characteristics (5 V) ................................ 15 Internal Power Dissipation (5 V) ............................. 16 External Power Dissipation (5 V) ............................ 17 ADSP-21060L/ADSP-21062L Specifications ................. 18 Operating Conditions (3.3 V) ................................. 18 Electrical Characteristics (3.3 V) ............................. 18 Internal Power Dissipation (3.3 V) .......................... 19 External Power Dissipation (3.3 V) .......................... 20 Absolute Maximum Ratings ................................... 20 ESD Caution ...................................................... 21 Package Marking Information ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC GENERAL DESCRIPTION ® The ADSP-2106x SHARC —Super Harvard Architecture Com- puter—is a 32-bit signal processing microcomputer that offers high levels of DSP performance. The ADSP-2106x builds on the ADSP-21000 DSP core to form a complete system-on-a-chip, adding a dual-ported on-chip SRAM and integrated I/O periph- erals supported by a dedicated I/O bus ...
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... SRAM. The internal memory is organized as two equal sized blocks of 1M bit each for the ADSP-21062/ ADSP-21062L and two equal sized blocks of 2M bits each for the ADSP-21060/ADSP-21060L. Each can be configured for dif- ferent combinations of code and data storage. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor or DMA controller ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 3 011 3 010 3 001 BUS PRIORITY RESET CLOCK ADSP-2106x #6 ADSP-2106x #5 ADSP-2106x #4 ADSP-2106x #3 ADDR31–0 CLKIN DATA47–0 RESET RPBA ID2–0 CONTROL 5 BR1–2, BR4–6 BR3 ADSP-2106x #2 ADDR31–0 CLKIN DATA47–0 RESET RPBA ID2–0 CONTROL CPA 5 BR1, BR3–6 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC DMA Controller The ADSP-2106x’s on-chip DMA controller allows zero-over- head data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simul- taneously executing its program instructions. DMA transfers can occur between the ADSP-2106x’s internal memory and external memory, external peripherals host processor ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Link Ports The ADSP-2106x features six 4-bit link ports that provide addi- tional I/O capabilities. The link ports can be clocked twice per cycle, allowing each to transfer eight bits of data per cycle. Link- port I/O is especially useful for point-to-point interprocessor communication in multiprocessing systems. ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC expert linker is fully compatible with existing linker definition file (LDF), allowing the developer to move between the graphi- cal and textual environments. In addition to the software development tools available from Analog Devices, third parties provide a wide range of tools sup- porting the SHARC processor family. Third party software tools include DSP libraries, real-time operating systems, and block diagram design tools ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC PIN FUNCTION DESCRIPTIONS The ADSP-2106x pin definitions are listed below. Inputs identi- fied as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchro- nously to CLKIN (or to TCK for TRST). Table 3. Pin Descriptions ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 3. Pin Descriptions (Continued) Pin Type Function ACK I/O/S Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The ADSP-2106x deasserts ACK as an output to add waitstates to a synchronous access of its internal memory multiprocessing system, a slave ADSP-2106x deasserts the bus master’ ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 3. Pin Descriptions (Continued) Pin Type Function TFSx I/O Transmit Frame Sync (Serial Ports 0, 1). RFSx I/O Receive Frame Sync (Serial Ports 0, 1). LxDAT3–0 I/O Link Port Data (Link Ports 0–5). Each LxDAT pin has internal pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register. ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TARGET BOARD CONNECTOR FOR EZ-ICE PROBE ® The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1JTAG test access port of the ADSP-2106x to monitor and control the target board processor during emulation. The EZ-ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST, TDI, TDO, EMU, and GND signals be made accessible on the target system via a 14-pin connector (a 2-row 7-pin strip header) such as that shown in Figure 5 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC OTHER JTAG CONTROLLER Figure 6. JTAG Scan Path Connections for Multiple ADSP-2106x Systems TDI EMU TCK TMS TRST TDO CLKIN ADSP-2106x #1 (OPTIONAL) TDI TDI TDO TDI EZ-ICE JTAG CONNECTOR TCK TMS EMU TRST TDO CLKIN OPTIONAL TDI TDO TDI TDO 5k * TDI ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADSP-21060/ADSP-21062 SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS (5 V) Parameter Description V Supply Voltage DD T Case Operating Temperature CASE High Level Input Voltage @ High Level Input Voltage @ Low Level Input Voltage @ V ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC INTERNAL POWER DISSIPATION (5 V) These specifications apply to the internal power portion of V only. For a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissi- pation Measurements.” Specifications are based on the operating scenarios. Operation Instruction Type ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC EXTERNAL POWER DISSIPATION (5 V) Total power dissipation has two components, one due to inter- nal circuitry and one due to the switching of external output drivers. Internal power dissipation is dependent on the instruc- tion execution sequence and the data operands involved. Internal power dissipation is calculated in the following way: ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ADSP-21060L/ADSP-21062L SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS (3.3 V) Parameter Description V Supply Voltage DD T Case Operating Temperature CASE High Level Input Voltage @ High Level Input Voltage @ Low Level Input Voltage @ Applies to input and bidirectional pins: DATA47– ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC INTERNAL POWER DISSIPATION (3.3 V) These specifications apply to the internal power portion of V only. For a complete discussion of the code used to measure power dissipation, see the technical note “SHARC Power Dissi- pation Measurements.” Specifications are based on the operating scenarios. Operation Instruction Type ...
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... EXT u 10 MHz u 10 0.037 MHz u 10 0.000 MHz u 10 0.010 MHz u 10 0.026 MHz u 10 0.001 W ADSP-21060L/ADSP-21060LC ADSP-21062L 3.3 V –0 +4 0.5 V –0 +0 0.5 V –0 0 200 pF –65qC to +150qC 280qC 130qC ). The write ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. ...
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... CK CLKIN t t CKH CKL Figure 9. Clock Input WRST Figure 10. Reset Rev Page March 2008 ADSP-21060L ADSP-21060L ADSP-21062L ADSP-21062L 40 MHz, 3 MHz, 3.3 V Min Max Min 25 100 30 1 8.75 8. and 3.3 V Min Max DT SRST ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Interrupts Table 11. Interrupts Parameter Timing Requirements t IRQ2–0 Setup Before CLKIN High SIR t IRQ2–0 Hold Before CLKIN High HIR t IRQ2–0 Pulse Width IPW 1 Only required for IRQx recognition in the following cycle. 2 Applies only if t and t requirements are not met. ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Flags Table 13. Flags Parameter Timing Requirements t FLAG3–0 IN Setup Before CLKIN High SFI t FLAG3–0 IN Hold After CLKIN High HFI t FLAG3–0 IN Delay After RD/WR Low DWRFI t FLAG3–0 IN Hold After RD/WR Deasserted HFIWR Switching Characteristics t FLAG3–0 OUT Delay After CLKIN High ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Memory Read—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the Table 14. Memory Read—Bus Master Parameter Timing Requirements t Address Selects Delay to Data Valid DAD Low to Data Valid ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Memory Write—Bus Master Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) without reference to CLKIN. These specifications apply when the ADSP-2106x is the Table 15. Memory Write—Bus Master Parameter Timing Requirements t ACK Delay from Address, Selects DAAK t ACK Delay from WR Low ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Synchronous Read/Write—Bus Master Use these specifications for interfacing to external memory sys- tems that require CLKIN—relative timing or for accessing a slave ADSP-2106x (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous memory reads and writes except where noted (see Memory Read— ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN t DADCCK ADDRCLK t DADRO ADDRESS, BMS, SW, MSx PAGE ACK (IN) READ CYCLE RD DATA (IN) WRITE CYCLE WR DATA (OUT) t ADRCK t t ADRCKH t DAAK t DPGC t DRWL t DRWL t SDDATO Figure 16. Synchronous Read/Write—Bus Master Rev Page March 2008 ADRCKL t HADRO t t HACK SACKC t DRDO ...
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... Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, t SRWLI 2 For ADSP-21060C specification is –3.5 – 5DT/16 ns min 7DT/16 ns max; for ADSP-21060LC specification is –3.75 – 5DT/16 ns min 7DT/16 ns max. 3 For ADSP-21062/ADSP-21062L/ADSP-21060C specification 5DT/16 ns max; for ADSP-21060LC specification is 19.25 + 5DT/16 ns max. 4 See Example System Hold Time Calculation on Page true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4 ...
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... CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN. 4 For ADSP-21060LC, specification is 8.5 – DT/8 ns max. 5 For ADSP-21060L, specification is 9.5 ns max, For ADSP-21060LC, specification is 11.0 ns max, For ADSP-21062L, specification is 8.75 ns max. 6 (O/D) = open drain, (A/D) = active drive. 7 For ADSP-21060C/ADSP-21060LC, specification 23DT/16 ns min. ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN HBR HBG (OUT) BRx (OUT) CPA (OUT, O/D) HBG (I N) BRx, CPA (IN RPBA HBR REDY (O/D) REDY (A/D) HBG (OUT O PEN DRAIN, A/D = ACTIVE DRIVE ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Asynchronous Read/Write—Host to ADSP-2106x Use these specifications for asynchronous host processor accesses of an ADSP-2106x, after the host has asserted CS and HBR (low). After HBG is returned by the ADSP-2106x, the host can drive the RD and WR pins to access the ADSP-2106x’s internal memory or IOP registers. HBR and HBG are assumed low for this timing ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN REDY (O/D) REDY (A/D) READ CYCLE ADDRESS/CS RD DATA (OUT) REDY ( REDY (A/D) WRITE CYCLE ADDRESS CS WR DATA (IN) REDY (O/D) REDY (A/D) O/D = OPEN DRAIN, A/D = ACTIVE DRIVE O/D = OPEN DRAIN, A/D = ACTIVE DRIVE Figure 19. Synchronous REDY Timing ATR YPR D ...
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... Memory Interface Disable Before HBG Low MTRHBG t Memory Interface Enable After HBG High MENHBG 1 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is –1.25 – DT/8 ns min, for ADSP-21062, specification is –1 – DT/8 ns min. 2 Strobes = RD, WR, PAGE, DMAG, BMS, SW. 3 For ADSP-21060LC, specification is 0.25 – DT/4 ns max addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write. ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN SBTS MEMORY INTERFACE DATA ACK ADRCLK Figure 22. Three-State Timing (Bus Transition Cycle, SBTS Assertion) t STSCK MIENA, MIENS, MIENHG t DATEN t ACKEN t ADCEN Rev Page March 2008 HTSCK MITRA, MITRS, MITRHG t DATTR t ACKTR t ADCTR ...
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... See Example System Hold Time Calculation on Page 47 5 For ADSP-21062/ADSP-21062L specification is –2.5 ns min max. 6 For ADSP-21060L/ADSP-21062L specification is –1 ns min. and DMAGx signals. For Paced Master mode, the data transfer is controlled by ADDR31–0, RD, WR, MS3–0, and ACK (not DMAG) ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC CLKIN t SDRLC DMARx DMAGx TRANSFERS BETWEEN ADSP-2106x INTERNAL MEMORY AND EXTERNAL DEVICE DATA (OUT) (FROM ADSP-2106x TO EXTERNAL DEVICE) DATA (IN) (FROM EXTERNAL DEVICE TO ADSP-2106x) TRANSFERS BETWEEN EXTERNAL DEVICE AND EXTERNAL MEMORY* (EXTERNAL HANDSHAKE MODE) WR (EXTERNAL DEVICE TO EXTERNAL MEMORY) RD (EXTERNAL MEMORY TO EXTERNAL DEVICE) ...
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... / DT/2 /2) + 1.25 ns max; for ADSP-21062L, specification / max; for ADSP-21062L, specification / max; for ADSP-21062L, specification /2) + 18.5 ns max. CK Rev Page March 2008 3.3 V Min Max DT/2 28.5 + DT/2 –3 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 25. Link Port Service Request Interrupts:1u and 2u Speed Operations Parameter Timing Requirements t LACK/LCLK Setup Before CLKIN Low SLCK t LACK/LCLK Hold After CLKIN Low HLCK 1 Only required for interrupt recognition in the current cycle. Link Ports —2 × CLK Speed Operation Calculation of link receiver data setup and hold relative to link ...
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... /4) – 1. / max; for ADSP-21060C/ADSP-21062L, specification / max; for ADSP-21060C, specification Rev Page March 2008 3.3 V Min Max 19 –6.5 8 2.25 –2 (t /4) – 0.75 (t / /4) – ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TRANSMIT CLKIN t DLCLK t t LCLKTWH LCLKTWL LCLK 1x OR LCLK 2x t DLDCH t HLDCH LDAT(3:0) OUT LACK (IN) t THE REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED. SLACH RECEIVE CLKIN t LCLKRWH LCLK 1x OR LCLK 2x LDAT(3:0) t DLAHC LACK (OUT) ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Serial Ports For serial ports, see Table 28, Table 29, Table 32, Table 33, Table 35, Figure 26, and mine whether communication is possible between two devices Table 28. Serial Ports—External Clock Parameter Timing Requirements t TFS/RFS Setup Before TCLK/RCLK SFSE t TFS/RFS Hold After TCLK/RCLK HFSE t Receive Data Setup Before RCLK ...
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... MFD = 0 t Data Enable from Late FS or MCE = 1, MFD = 0 DDTENFS 1 MCE = 1, TFS enable and TFS valid follow t DDTLFSE 2 For ADSP-21062/ADSP-21062L, specification is 12.75 ns max; for ADSP-21060L/ADSP-21060LC, specification is 12.8 ns max. 3 For ADSP-21060/ADSP-21060C, specification min – min, 0. max. ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC DATA RECEIVE— INTERNAL CLOCK DRIVE EDGE t SCLKIW RCLK t DFSE t t SFSI HOFSE RFS t SDRI DR NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE. DATA TRANSMIT— INTERNAL CLOCK DRIVE EDGE t SCLKIW TCLK t DFSI ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC RCLK RFS DT TCLK TFS DT EXTERNAL RFS WITH MCE = 1, MFD = 0 DRIVE SAMPLE DRIVE t t SFSE/I HOFSE/I t DDTE HDTE/I DDTENFS 1ST BIT t DDTLFSE LATE EXTERNAL TFS DRIVE SAMPLE DRIVE t HOFSE/I t SFSE/I t DDTE/I TDDTENFS t HDTE/I 1ST BIT t DDTLFSE Figure 26. Serial Ports—External Late Frame Sync Rev ...
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... TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET. 2 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is 18.5 ns min. 3 System Outputs = DATA63–0, ADDR31–0, MS3–0, RD, WR, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7– ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC TEST CONDITIONS For the ac signal specifications (timing parameters), see Specifications on Page 21. These specifications include output disable time, output enable time, and capacitive loading. The timing specifications for the DSP apply for the voltage reference levels in Figure 28. INPUT OR 1.5V OUTPUT Figure 28. Voltage Reference Levels for AC Measurements (Except Output ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Output Characteristics ( 5.25V, - 40°C 5.0V, +25°C 0 4.75V, +100° 4.75V,+100° 5.0V, +25° 100 - 125 - 150 0 0.75 1.50 2.25 3.00 SOURCE VOLTAGE - V Figure 31. ADSP-21062 Typical Output Drive Currents (V 16.0 14.0 12.0 RISE TIME 10 0.005x + 3.7 8.0 FALL TIME 6.0 4.0 2 0.0031x + 1 100 120 LOAD CAPACITANCE - pF Figure 32. Typical Output Rise Time (10% to 90% V ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Output Characteristics (3.3 V) 100 3.3V, +25° 3.0V, +85° 3.0V, +85°C 3.3V, +25° 100 OL - 120 0.5 1.0 1.5 2.0 Figure 35. ADSP-21062 Typical Output Drive Currents ( 0.0329x - 1. NOMINAL - 100 125 LOAD CAPACITANCE - pF Figure 36. Typical Output Delay or Hold vs. Load Capacitance (at Maximum Case Temperature 3.6V, - 40° ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ENVIRONMENTAL CONDITIONS The ADSP-2106x processors are rated for performance under T environmental conditions specified in the CASE ditions ( Page 15 and Operating Conditions (3 Page 18. Thermal Characteristics for MQFP_PQ4 and PBGA Packages The ADSP-21060/ADSP-21060L and ADSP-21062/ADSP- 21062L are available in 240-lead thermally enhanced MQFP_PQ4 and 225-ball plastic ball grid array packages ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 225-BALL PBGA BALL CONFIGURATIONS Table 40. ADSP-2106x 225-Ball Metric PBGA Ball Assignments (B-225-2) Pin PBGA Pin Name Pin Number Name BMS A01 ADDR25 ADDR30 A02 ADDR26 DMAR2 A03 MS2 DT1 A04 ADDR29 RCLK1 A05 DMAR1 TCLK0 A06 TFS1 RCLK0 A07 CPA ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC BR3 DATA42 DATA44 DATA47 BR2 DATA39 DATA43 DATA45 DATA36 DATA38 DATA41 DATA46 DATA34 DATA35 DATA37 DATA40 DATA31 DATA32 DATA30 DATA33 DATA27 DATA28 DATA26 DATA29 DATA23 DATA24 DATA25 DATA22 DATA20 DATA21 DATA19 DATA18 DATA17 DATA16 DATA15 DATA12 DATA14 DATA13 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 240-LEAD MQFP_PQ4/CQFP PIN CONFIGURATIONS Table 41. ADSP-2106x MQFP_PQ4, ADSP-21060CW, and ADSP-21060LCW CQFP Pin Assignments (SP-240-2, QS-240-2) Pin Name Pin No. Pin Name Pin No. TDI 1 ADDR20 41 TRST 2 ADDR21 GND 43 DD TDO 4 ADDR22 44 TIMEXP 5 ADDR23 45 EMU 6 ADDR24 46 ICSA FLAG3 8 GND 48 FLAG2 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Table 42. ADSP-21060CZ/21060LCZ CQFP Pin Assignments (QS-240-1) Pin Name Pin No. Pin Name Pin No. GND 1 DATA29 41 DATA0 2 GND 42 DATA1 3 DATA30 43 DATA2 4 DATA31 DATA32 45 DD DATA3 6 GND 46 DATA4 DATA5 GND 9 DATA33 49 DATA6 10 DATA34 50 DATA7 11 DATA35 51 DATA8 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC OUTLINE DIMENSIONS 2.70 MAX 23.20 23.00 SQ 22.80 BALL A1 INDICATOR 18.00 20.10 BSC SQ 20.00 SQ TOP VIEW 19.90 1.27 BSC 0. PLACES DETAIL A 0.70 0.60 0.50 SEATING PLANE BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MS-034-AAJ-2 Figure 40. 225-Ball Plastic Ball Grid Array [PBGA] (B-225-2) Dimensions shown in millimeters Rev Page March 2008 A1 CORNER INDEX AREA ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 0.66 0.56 0.46 SEATING PLANE 3.50 3.40 0.20 3.30 0.09 0.38 7° 0.25 0° 0.076 COPLANARITY VIEW A ROTATED 90° CCW Figure 41. 240-Lead Metric Quad Flat Package, Thermally Enhanced “PowerQuad” [MQFP_PQ4] 34.60 BSC SQ 29.50 REF 4.10 3.78 3.55 240 1 PIN 1 HEAT SLUG TOP VIEW (PINS DOWN VIEW A 0.27 MAX 0.50 BSC 0.17 MIN LEAD PITCH COMPLIANT WITH JEDEC STANDARDS MS-029-GA ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 36.60 36.13 SQ 35.65 32.00 BSC SQ PIN 1 240 INDICATOR 1 TOP VIEW (PINS DOWN) HEAT SLUG 60 61 19.00 REF SQ 4.30 3.62 2.95 7° 0.90 0.23 -3° 0.75 0.20 0.60 0.17 NOTES: 1. LEAD FINISH = GOLD PLATE 2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX (Sweep and/or Offset can be used as the controlling dimension). Figure 42. 240-Lead Ceramic Quad Flat Package, Heat Slug Up [CQFP] ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 75.00 BSC SQ 29.50 BSC 2.05 120 121 65.90 BSC TOP VIEW HEAT SLUG 180 181 75.50 BSC SQ 0.50 3.42 SIDE VIEW 3.17 2.92 Figure 43. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Down [CQFP] 2.60 2.55 2.50 3.60 3.55 3. 29.50 BSC 1 INDEX 1 240 INDEX 2 GOLD 1.50 DIA PLATED NO GOLD 1.22 (4×) 0.90 0.80 0.70 (QS-240-2B) Dimensions shown in millimeters Rev Page March 2008 16.50 (8× ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 36.60 36.13 SQ 35.65 32.00 BSC SQ PIN 1 240 INDICATOR 1 SEAL RING LID TOP VIEW (PINS DOWN 28.05 27.80 SQ 27.55 4.20 3.52 2.85 7° 0.90 0.23 -3° 0.75 0.20 0.60 0.17 NOTES: 1. LEAD FINISH = GOLD PLATE 2. LEAD SWEEP/LEAD OFFSET = 0.013mm MAX (Sweep and/or Offset can be used as the controlling dimension). Figure 44. 240-Lead Ceramic Quad Flat Package, Heat Slug Down [CQFP] ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC 75.00 BSC SQ 29.50 BSC 2.05 120 121 SEAL RING LID 65.90 BSC TOP VIEW 180 181 75.50 BSC SQ 0.50 3.42 SIDE VIEW 3.17 2.92 Figure 45. 240-Lead Ceramic Quad Flat Package, Mounted with Cavity Up [CQFP] SURFACE-MOUNT DESIGN Table 43 is provided as an aide to PCB design. For industry- standard design recommendations, refer to IPC-7351, Generic Requirements for Surface-Mount Design and Land Pattern Standard ...
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... ADSP-21062LKS-160 0qC to 85qC 2 ADSP-21062LKSZ-160 0qC to 85qC ADSP-21062LKB-160 0qC to 85qC 2 ADSP-21062LKBZ-160 0qC to 85qC ADSP-21062LAB-160 –40qC to 85qC 2 ADSP-21062LABZ-160 –40qC to 85qC ADSP-21062LCS-160 –40qC to +100qC 40 MHz 2 ADSP-21062LCSZ-160 –40qC to +100qC 40 MHz 1 Model refers to package with formed leads. For model numbers of unformed lead versions (QS-240-1B, QS-240-2B), contact Analog Devices or an Analog Devices sales representative ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev Page March 2008 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC Rev Page March 2008 ...
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... ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00167-0-3/08(F) Rev Page March 2008 ...