LC5512MV Lattice Semiconductor Corp., LC5512MV Datasheet
LC5512MV
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LC5512MV Summary of contents
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... I/Os Packages © 2006 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com ...
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Lattice Semiconductor Figure 1. ispXPLD 5000MX Block Diagram V CCO0 V REF0 sysIO Bank 0 GCLCK0 V CCP sysCLOCK PLL 0 GNDP GCLK1 sysIO Bank 1 Optional sysCONFIG Interface V REF1 V CCO1 Introduction The ispXPLD 5000MX family represents a ...
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Lattice Semiconductor 5000MX. Incoming signals may connect to the global routing pool or the registers in the MFBs. An Output Sharing Array (OSA) increases the number of I/O available to each MFB, allowing a complete function high-performance access to the ...
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Lattice Semiconductor Cascading For Wide Operation In several modes it is possible to cascade adjacent MFBs to support wider operation. Table 2 details the different cascading options. There are chains of MFBs in each device which determine those MFBs that ...
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Lattice Semiconductor Figure 3. MFB in SuperWIDE Logic Mode† 68 Inputs Routing 68 Inputs Adjacent Figure 4. Macrocell Slice in Logic Mode AND-Array From GRP 68 AND Array Dual-OR Array from from MFB Shared PT Clk Shared PT Clk En ...
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Lattice Semiconductor AND-Array The programmable AND-Array consists of 68 inputs and 164 output product terms. The 68 inputs from the GRP are used to form 136 lines in the AND-Array (true and complement of the inputs). Each line in the ...
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Lattice Semiconductor Figure 6. Dual-OR PT Sharing Array From PT0 From PT1 From PT2 From PT3 From PT4 Product Term Sharing Array The Product Term Sharing Array (PTSA) consists of 32 inputs from the Dual-OR Array (Expandable PTSA OR) and ...
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Lattice Semiconductor Macrocell The 32 registered macrocells in the MFB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch flip-flop and the necessary clocks and control ...
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Lattice Semiconductor Table 4. MFB Memory Configuration Dual-port Single-port, Pseudo Dual Port, FIFO CAM 1. Smaller configurations are possible. Input and Output The data input and control signals to a MFB in memory mode are generated from inputs from the ...
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Lattice Semiconductor True Dual-Port SRAM Mode In Dual-Port SRAM Mode the multi-function array is configured as a dual port SRAM. In this mode two independent read/write ports access the same 8,192-bits of memory. Data widths ...
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Lattice Semiconductor Pseudo Dual-Port SRAM Mode In Pseudo Dual-Port SRAM Mode the multi-function array is configured as a SRAM with an independent read and write ports that access the same 16,384-bits of memory. Data widths ...
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Lattice Semiconductor Single-Port SRAM Mode In Single-Port SRAM Mode the multi-function array is configured as a single-port SRAM. In this mode one ports accesses 16,384-bits of memory. Data widths and 32 are supported by ...
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Lattice Semiconductor FIFO Mode In FIFO Mode the multi-function array is configured as a FIFO (First In First Out) buffer with built in control. The read and write clocks can be different or the same dependent on the application. Four ...
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Lattice Semiconductor CAM Mode In CAM Mode the multi-function array is configured as a Ternary Content Addressable Memory (CAM). CAM behaves like a reverse memory where the input is data and the output is an address. It can be used ...
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Lattice Semiconductor Clock Distribution The ispXPLD 5000MX family has four dedicated clock input pins: GCLK0-GCLK3. GLCK0 and GCLK3 can be routed through a PLL circuit or routed directly to the internal clock nets. The internal clock nets (CLK0-CLK3) are directly ...
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Lattice Semiconductor Figure 15. PLL Block Diagram Input Clock CLK_IN (M) Divider PLL_RST PLL_FBK Figure 16. Connection of Optional PLL Inputs and Outputs To GRP PLL_LOCK CLK_OUT From Macrocell To GRP PLL_RST To GRP From Macrocell To GRP PLL_FBK From ...
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Lattice Semiconductor Output Sharing Array (OSA) A number of I/O pads are available in each sysIO bank to route the selected number of macrocells from the MFB outputs directly to the I/O pads in logic mode. In the ispXPLD 5000MX, ...
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Lattice Semiconductor Figure 17. I/O Cell Shared PTOE 0 Shared PTOE 1 Shared PTOE 2 Shared PTOE 3 Data Output from Primary Macrocell Data Output from Alternate Macrocells To Primary Macrocell To Alternate Macrocell Table 10. Shared PTOE Segments ispXPLD ...
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Lattice Semiconductor Table 12. ispXPLD 5000MX Supported I/O Standards sysIO Standard LVTTL LVCMOS-3.3 LVCMOS-2.5 LVCMOS-1.8 PCI 3.3V AGP-1X SSTL3, Class I & II SSTL2, Class I & II CTT 3.3 CTT 2.5 HSTL, Class I HSTL, Class III HSTL, Class ...
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Lattice Semiconductor Programmable Slew Rate The slew rate of outputs is carefully controlled. When outputs are configured as LVCMOS the devices support two slew rates. This allows system noise and performance to be balanced in a design. Programmable Bus-Maintenance All ...
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Lattice Semiconductor sysCONFIG Interface In addition to being able to program the device through the IEEE 1532 interface a microprocessor style interface (sysCONFIG interface) allows reconfiguration of the SRAM bits within the device. For more information on the sysCONFIG capability, ...
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Lattice Semiconductor Absolute Maximum Ratings Supply Voltage ( -0 ...
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Lattice Semiconductor DC Electrical Characteristics Symbol Parameter Input or I/O Leakage IL Input High Leakage Current I/O Active Pullup Current PU I I/O Active Pulldown Current PD I Bus Hold Low ...
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Lattice Semiconductor Supply Current Symbol Parameter ispXPLD 5256 1,2 I Operating Power Supply Current CC Standby Power Supply Current I CCO (per I/O Bank) PLL Power Supply Current I CCP (per PLL Bank) Standby IEEE 1149.1 TAP Power I CCJ ...
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Lattice Semiconductor Supply Current (Continued) Symbol Parameter ispXPLD 51024 1,2 I Operating Power Supply Current CC Standby Power Supply Current I CCO (per I/O Bank) PLL Power Supply Current I CCP (per PLL Bank) Standby IEEE 1149.1 TAP Power I ...
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Lattice Semiconductor sysIO Recommended Operating Conditions Standard Min. LVCMOS 3.3 3.0 LVCMOS 2.5 2.3 1 LVCMOS 1.8 1.65 LVTTL 3.0 PCI 3.3 3.0 AGP-1X 3.15 SSTL 2 2.3 SSTL 3 3.0 CTT 3.3 3.0 CTT 2.5 2.3 HSTL Class I ...
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Lattice Semiconductor sysIO Single Ended DC Electrical Characteristics V IL Input/Output Standard Min (V) Max (V) LVCMOS 3.3 -0.3 LVTTL -0.3 LVCMOS 2.5 -0 LVCMOS 1.8 -0.3 0.68 3 LVCMOS 1.8 -0.3 0.68 4 PCI 3.3 -0.3 1.08 ...
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Lattice Semiconductor sysIO Differential DC Electrical Characteristics Parameter Description LVDS V Input Voltage INP V Differential Input Threshold THD I Input Current IN V Output High Voltage for Output Low Voltage for Output Voltage ...
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Lattice Semiconductor ispXPLD 5000MX Family External Switching Characteristics Parameter Description Data Propagation Delay 5-PT Bypass t Data propagation delay PD_PTSA MFB Register Setup Time t S Before Clock, 5-PT Bypass MFB Register Setup Time t S_PTSA Before Clock ...
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Lattice Semiconductor ispXPLD 5000MX Family External Switching Characteristics (Continued) Parameter Description Clock Frequency to RAM in: Single Port Mode 5 f (RAM) MAX Dual Port Mode Pseudo Dual Port Mode 5 f (FIFO) Clock Frequency to FIFO MAX t Power-on ...
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Lattice Semiconductor Timing Model The task of determining timing in a ispXPLD 5000MX device is relatively simple. The timing model show in Figure 20 shows the specific delay paths. Once the implementation of a given function is determined either con- ...
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Lattice Semiconductor ispXPLD 5000MX Family Internal Switching Characteristics Parameter Description In/Out Delays t Input Buffer Delay IN Global Clock Input t GCLK_IN Buffer Delay Global RESET Pin t RST Delay Global OE Pin t GOE Delay Delay through t BUF ...
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Lattice Semiconductor ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Parameter Description Registered Delays D-Register Setup t S Time, Global Clock D-Register Setup t S_PT Time, PT Clock D-Register Hold t H Time Register Clock to t COi OSA Time Clock ...
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Lattice Semiconductor ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Parameter Description Additional Delay for t PT Cascading CASC between MFBs Carry Chain Delay, t CICOMFB MFB to MFB Carry Chain Delay, t Macro-Cell to CICOMC Macro-Cell Routing Delay for t ...
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Lattice Semiconductor ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Parameter Description Write-Enable setup t FIFOWES before Write Clock Write-Enable hold t FIFOWEH after Write Clock Read-Enable setup t FIFORES before Read Clock Read-Enable hold t FIFOREH after Read Clock Reset ...
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Lattice Semiconductor ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Parameter Description Write Mask t Register Setup CAMWMSKS Time before Clock Write Mask t Register Setup CAMWMSKH Time after Clock Reset to CAM t CAMRSTO Output Delay Reset Recovery t CAMRSTR ...
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Lattice Semiconductor ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Parameter Description Address Hold time t SPADDH after Clock Time R/W Setup before t SPRWS Clock Time R/W Hold time after t SPRWH Clock Time Data Setup before t SPDATAS Clock ...
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Lattice Semiconductor ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Parameter Description R/W Hold time after t PDPRWH Clock Time Data Setup before t PDPDATAS Clock Time Data Hold time after t PDPDATAH Clock Time Read Clock to t PDPRCLKO Output ...
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Lattice Semiconductor ispXPLD 5000MX Family Internal Switching Characteristics (Continued) Parameter Description Clock Enable B t Setup before Clock DPCEBS B Time Clock Enable Hold t B after Clock B DPCEBH Time Address B Setup t DPADDBS before Clock B Time ...
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Lattice Semiconductor ispXPLD 5000MX Family Timing Adders Parameter Description t Input Adjusters IOI LVTTL_in Using 3.3V TTL Using 1.8V LVCMOS_18_in CMOS Using 2.5V LVCMOS_25_in CMOS Using 3.3V LVCMOS_33_in CMOS AGP_1X_in Using AGP 1x CTT25_in Using CTT 2.5V CTT33_in Using CTT ...
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Lattice Semiconductor ispXPLD 5000MX Family Timing Adders (Continued) Parameter Description Using 1.8V LVCMOS_18_8mA_out CMOS Standard, 8mA Drive Using 1.8V LVCMOS_18_12mA_out CMOS Standard, 12mA Drive Using 2.5V LVCMOS_25_4mA_out CMOS Standard, 4mA Drive Using 2.5V LVCMOS_25_5.33mA_out CMOS Standard, 5.33 mA Drive Using ...
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Lattice Semiconductor ispXPLD 5000MX Family Timing Adders (Continued) Parameter Description Using HSTL 2.5V, HSTL_I_out Class I Using HSTL 2.5V, HSTL_III_out Class III Using HSTL 2.5V, HSTL_IV_out Class IV Using Low Voltage Differen- LVDS_out tial Signaling (LVDS) Using Low LVPECL_out Voltage ...
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Lattice Semiconductor sysCLOCK PLL Timing Symbol Parameter t Input clock, high time PWH t Input clock, low time PWL Input Clock, rise and fall time Input clock stability, cycle to cycle (peak) INSTB f ...
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Lattice Semiconductor ispXP sysCONFIG Port Timing Specifications Symbol sysCONFIG Write Cycle Timing t Input setup time CCLK rise SUCS t Hold time CCLK rise HCS t Input setup time of write data to CCLK ...
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Lattice Semiconductor Boundary Scan Timing Specifications Parameter t TCK [BSCAN] clock pulse width BTCP t TCK [BSCAN] clock pulse width high BTCPH t TCK [BSCAN] clock pulse width low BTCPL t TCK [BSCAN] setup time BTS t TCK [BSCAN] hold ...
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Lattice Semiconductor Power Consumption ispXPLD 5000MC Typical I 800 700 600 500 400 300 200 100 0 0 100 Operating Frequency (MHz) Note: The device is configured with maximum number of 16-bit counters, no PLL, typical current at 1.8V, 25°C. ...
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Lattice Semiconductor • K11 = Current per column driver (µA/MHz) Power Estimation Equations ICC = ICC_DC + IMFB_CPLD + IMFB_ SRAM/PDPRAM/FIFO + IMFB_DPRAM + IMFB_CAM + IPLL_D ICC_DC Use the appropriate value for 5000MC (1.8V power supply) or 5000MV/B (2.5V/3.3V ...
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Lattice Semiconductor Switching Test Conditions Figure 21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance, voltage, and other test conditions are shown in Table 14. Figure 21. Output Test Load, LVTTL ...
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Lattice Semiconductor Signal Descriptions Signal Names TMS TCK TDI TDO TOE GOE0, GOE1 RESET yzz GND CCO0, CCO1, CCO2, CCO3 REF0, REF1, REF2, REF3 GCLK0, GCLK1, GCLK2, GCLK3 CLK_OUT0, ...
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Lattice Semiconductor ispXPLD 5000MX Power Supply and NC Connections 4 Signals 208 PQFP 256 fpBGA VCC 10, 49, 76, 114, D4, D13, F6, F11, L6, 153, 180 L11, N4, N13 VCCO0 5, 17, 189, 204 A1, F7, G6 VCCO1 42, ...
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Lattice Semiconductor ispXPLD 5256MX Logic Signal Connections Primary Macrocell/ sysIO Bank LVDS Pair Function 0 61N 0 61P 0 62N 0 62P 0 63N 0 63P - - 0 64N 0 64P H18/CLK_OUT0 0 65N 0 65P - - 0 ...
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Lattice Semiconductor ispXPLD 5256MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 1 4N A16/CSB 1 5P A18/READ 1 5N A20/CCLK - - - - PROGRAMB - ...
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Lattice Semiconductor ispXPLD 5256MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 2 20P 2 20N C16/VREF2 2 21P 2 21N 2 22P 2 22N 2 23P 2 23N 2 24P 2 24N - - - - ...
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Lattice Semiconductor ispXPLD 5256MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 3 34N 3 34P 3 35N 3 35P E24/PLL_FBK1 3 36N E22/PLL_RST1 3 36P - - GND (Bank 3) 3 37N - - 3 37P ...
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Lattice Semiconductor ispXPLD 5256MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 3 51N 3 51P 0 52N 0 52P - - 0 53N 0 53P 0 54N - - 0 54P - - GND (Bank 0) ...
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Lattice Semiconductor ispXPLD 5512MX Logic Signal Connections sysIO LVDS Primary Macrocell/ Bank Pair Function 0 109N O30 0 109P O28 0 110N O26 0 110P O24 0 111N O22 — — V CCO0 0 111P O20 — — GND (Bank ...
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Lattice Semiconductor ispXPLD 5512MX Logic Signal Connections (Continued) sysIO LVDS Primary Macrocell/ Bank Pair Function — GCLK0N GCLK1 — — GND — — TDI — — TMS — — TCK — — TDO 1 0P A0/DATA0 1 0N A2/DATA1 1 ...
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Lattice Semiconductor ispXPLD 5512MX Logic Signal Connections (Continued) sysIO LVDS Primary Macrocell/ Bank Pair Function 1 13P B24 — — V CCO1 1 13N B26 1 14P B28 1 14N B30 1 15P C0 1 15N C2 1 16P C4 ...
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Lattice Semiconductor ispXPLD 5512MX Logic Signal Connections (Continued) sysIO LVDS Primary Macrocell/ Bank Pair Function — — V CCO2 2 29N E10 — — GND (Bank 2) 2 30P E12 2 30N E16 2 31P E18 2 31N E20/V REF2 ...
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Lattice Semiconductor ispXPLD 5512MX Logic Signal Connections (Continued) sysIO LVDS Primary Macrocell/ Bank Pair Function 2 47N G26 — — GND (Bank 2) 2 48P G28 2 48N G30 2 49P H0 2 49N H2 2 50P H4 — — ...
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Lattice Semiconductor ispXPLD 5512MX Logic Signal Connections (Continued) sysIO LVDS Primary Macrocell/ Bank Pair Function 3 61N I14 3 61P I12 3 62N I10 3 62P I8/CLK_OUT1 3 63N I6 — — 63P I4 3 64N I2 ...
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Lattice Semiconductor ispXPLD 5512MX Logic Signal Connections (Continued) sysIO LVDS Primary Macrocell/ Bank Pair Function 3 79N K8 3 79P K6 3 80N K5 3 80P K4 3 81N K2 3 81P K0 — — GND (Bank 3) 3 82N ...
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Lattice Semiconductor ispXPLD 5512MX Logic Signal Connections (Continued) sysIO LVDS Primary Macrocell/ Bank Pair Function 0 96N M12 0 96P M10 0 97N M8 0 97P M6 0 98N M5 0 98P M4 0 99N M2 — — V CCO0 ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections Primary Macrocell/ sysIO Bank LVDS Pair Function 0 127N S22 0 127P S20 0 128N S18 0 128P S16 0 129N S14 - - VCCO0 0 129P S12 - - GND (Bank 0) ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 0 143N U22 - - VCCO0 0 143P U20 - - GND (Bank 0) 0 144N U18 0 144P U16 0 145N U14 0 145P ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function - - TCK - - TDO 1 0P A30/DATA0 1 0N A28/DATA1 1 1P A26/DATA2 1 1N A24/DATA3 1 2P A22/DATA4 1 2N A20/DATA5 - ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 1 - C28 - - GND (Bank 1) 1 15P C26 - - VCCO1 1 15N C24 - - GND 1 16P C22 - - ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 2 29N GND 2 30P E4 2 30N E6 2 31P VCCO2 2 31N E10 - - GND (Bank ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 2 46N G6 2 47P VCCO2 2 47N G10 - - GND (Bank 2) 2 48P G12 2 48N G14 2 49P ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function - GCLK3N GCLK2 - - VCCP - GCLK3P GCLK3 3 61N J0 3 61P J2 3 62N J4 3 62P J6 3 63N J8 3 ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 3 76P L30/PLL_FBK1 3 77N M0/PLL_RST1 3 77P - - GND (Bank 3) 3 78N - - VCCO3 3 78P - - GND 3 79N ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 3 93N 3 93P - - GND (Bank 3) 3 94N - - VCCO3 3 94P - - GND 3 95N - - VCC 3 ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function - - VCC 0 109P Q28 - - GND 0 110N Q26 0 110P Q24 0 111N Q22 - - VCCO0 0 111P Q20 - ...
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Lattice Semiconductor ispXPLD 5768MX Logic Signal Connections (Continued) Primary Macrocell/ sysIO Bank LVDS Pair Function 0 126N S26 0 126P S24 Global Clock LVDS pair options: GCLK0 and GCLK1, as well as GCLK2 and GCLK3, can be paired together to ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections sysIO Primary Bank LVDS Pair Macrocell/Function 0 159N AA22 0 159P AA20 0 160N AA18 0 160P AA16 0 161N AA14 - - VCCO0 0 161P AA12 - - GND (Bank 0) 0 ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function 0 175N AC22 - - VCCO0 0 175P AC20 - - GND (Bank 0) 0 176N AC18 0 176P AC16 0 177N AC14 0 177P AC12 ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function - - - - TDO GND (Bank ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function 1 15N 1 16P E30/DATA0 1 16N E28/DATA1 1 17P E26/DATA2 1 17N E24/DATA3 1 18P E22/DATA4 1 18N E20/DATA5 - - GND (Bank 1) 1 ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function - - GND (Bank 1) 1 31P G26 - - VCCO1 1 31N G24 - - GND 1 32P G22 - - VCC 1 32N G20 ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function - - GND 2 46P 2 46N 2 47P - - VCCO2 2 47N I10 - - GND (Bank 2) 2 48P I12 2 48N I14 ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function 2 63P - - VCCO2 2 63N K10 - - GND (Bank 2) 2 64P K12 2 64N K14 2 65P K16 2 65N K18 2 ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function - - VCCO2 2 79N N10 - - GND (Bank 2) 2 80P N12 2 80N N14 2 81P N16 2 81N N18 2 82P N20 ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function - GCLK3P GCLK3 3 93N 3 93P 3 94N 3 94P 3 95N 3 95P R10 - - GND (Bank 3) 3 96N R12 - - ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function - - GND (Bank 3) 3 110N - - VCCO3 3 110P - - GND 3 111N 3 111P U10 3 112N U12 3 112P U14/CLK_OUT1 ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function 3 126N VCCO3 3 126P GND 3 127N VCC 3 127P W10 3 128N W12 3 128P ...
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Lattice Semiconductor ispXPLD 51024MX Logic Signal Connections (Continued) sysIO Primary Bank LVDS Pair Macrocell/Function 0 142N Y26 0 142P Y24 0 143N Y22 - - VCCO0 0 143P Y20 - - GND (Bank 0) 0 144N Y18 0 144P Y16 ...
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Lattice Semiconductor Part Number Description Device Family LC Device Number 5256 = 256 Macrocells 5512 = 512 Macrocells 5768 = 768 Macrocells 51024 = 1,024 Macrocells Memory M Supply Voltage 1.8V Speed ...
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Lattice Semiconductor ispXPLD 5000MC (1.8V) Commercial Devices (Continued) Device Part Number LC51024MC-52F484C LC51024MC-75F484C LC51024MC LC51024MC-52F672C LC51024MC-75F672C Device Part Number LC5256MC-5F256I LC5256MC LC5256MC-75F256I LC5512MC-75Q208I LC5512MC LC5512MC-75F256I LC5512MC-75F484I LC5768MC-75F256I LC5768MC LC5768MC-75F484I LC51024MC-75F484I LC51024MC LC51024MC-75F672I Device Part Number LC5256MB-4F256C LC5256MB LC5256MB-5F256C LC5256MB-75F256C LC5512MB-45Q208C ...
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... LC5256MV-75F256C LC5512MV-45Q208C LC5512MV-75Q208C LC5512MV-45F256C LC5512MV LC5512MV-75F256C LC5512MV-45F484C LC5512MV-75F484C LC5768MV-5F256C LC5768MV-75F256C LC5768MV LC5768MV-5F484C LC5768MV-75F484C LC51024MV-52F484C LC51024MV-75F484C LC51024MV LC51024MV-52F672C LC51024MV-75F672C Device Part Number LC5256MV-5F256I LC5256MV LC5256MV-75F256I LC5512MV-75Q208I LC5512MV LC5512MV-75F256I LC5512MV-75F484I LC5768MV-75F256I LC5768MV LC5768MV-75F484I LC51024MV-75F484I LC51024MV LC51024MV-75F672I Macrocells Voltage (V) t (ns) PD 512 2.5 7.5 512 2.5 7.5 512 2.5 7.5 768 2 ...
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Lattice Semiconductor Lead-Free Packaging ispXPLD 5000MC (1.8V) Lead-Free Commercial Devices Device Part Number LC5256MC-4FN256C LC5256MC LC5256MC-5FN256C LC5256MC-75FN256C LC5512MC-45QN208C LC5512MC-75QN208C LC5512MC-45FN256C LC5512MC LC5512MC-75FN256C LC5512MC-45FN484C LC5512MC-75FN484C LC5768MC-5FN256C LC5768MC-75FN256C LC5768MC LC5768MC-5FN484C LC5768MC-75FN484C LC51024MC-52FN484C LC51024MC-75FN484C LC51024MC LC51024MC-52FN672C LC51024MC-75FN672C ispXPLD 5000MC (1.8V) Lead-Free Industrial Devices ...
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... LC5512MB-75FN256I LC5512MB-75FN484I LC5768MB-75FN256I LC5768MB LC5768MB-75FN484I LC51024MB-75FN484I LC51024MB LC51024MB-75FN672I ispXPLD 5000MV (3.3V) Lead-Free Commercial Devices Device Part Number LC5256MV-4FN256C LC5256MV LC5256MV-5FN256C LC5256MV-75FN256C LC5512MV-45QN208C LC5512MV-75QN208C LC5512MV-45FN256C LC5512MV LC5512MV-75FN256C LC5512MV-45FN484C LC5512MV-75FN484C ispXPLD 5000MX Family Data Sheet Macrocells Voltage (V) t (ns) PD 256 2.5 4.0 256 2.5 5.0 256 2.5 7.5 512 2.5 4.5 512 2.5 7 ...
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... Lead-Free Industrial Devices Device Part Number LC5256MV-5FN256I LC5256MV LC5256MV-75FN256I LC5512MV-75QN208I LC5512MV LC5512MV-75FN256I LC5512MV-75FN484I LC5768MV-75FN256I LC5768MV LC5768MV-75FN484I LC51024MV-75FN484I LC51024MV LC51024MV-75FN672I For Further Information In addition to this data sheet, the following technical notes may be helpful when designing with the ispXPLD 5000MX family: • ...