DS90CR483 National Semiconductor, DS90CR483 Datasheet
DS90CR483
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DS90CR483 Summary of contents
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... DS90CR483 / DS90CR484 48-Bit LVDS Channel Link SER/DES — 112 MHz General Description The DS90CR483 transmitter converts 48 bits of CMOS/TTL data into eight LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a ninth LVDS link. Every cycle of the transmit clock 48 bits of input data are sampled and transmitted ...
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... Generalized Transmitter Block Diagram Generalized Receiver Block Diagram Ordering Information Order Number DS90CR483VJD DS90CR484VJD www.national.com Function Transmitter (Serializer) Receiver (Deserializer) 2 10091802 10091803 Package VJD100A VJD100A ...
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... Input Current IN I Output Short Circuit OS Current (Note 1) DS90CR484VJD Package Derating: DS90CR483VJD DS90CR484VJD −0.3V to +4V ESD Rating: −0.3V to +5.5V DS90CR483 (HBM, 1.5kΩ, 100pF) + 0.3V) (EIAJ, 0Ω, 200pF) CC DS90CR484 −0.3V to +3.6V (HBM, 1.5kΩ, 100pF) (EIAJ, 0Ω, 200pF) −0.3V to +3.6V Recommended Operating Continuous Conditions +150˚C −65˚C to +150˚C ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter LVDS DRIVER DC SPECIFICATIONS |V | Differential Output OD Voltage ∆V Change between Complimentary Output States V Offset Voltage OS ∆V Change ...
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Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter LLHT LVDS Low-to-High Transition Time, (Figure 2), PRE = 0.75V (disabled) LVDS Low-to-High Transition Time, (Figure 2), PRE = Vcc (max) LHLT LVDS High-to-Low Transition ...
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Chipset RSKM Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 4, 7). See Applications Infor- mation section for more details on this parameter and how to apply it. Symbol Parameter RSKM Receiver Skew Margin without Deskew in ...
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... AC Timing Diagrams Note 9: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. FIGURE 2. DS90CR483 (Transmitter) LVDS Output Load and Transition Times FIGURE 3. DS90CR484 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 4. DS90CR483 (Transmitter) Input Clock Transition Time 10091810 FIGURE 1. “ ...
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... AC Timing Diagrams FIGURE 5. DS90CR483 (Transmitter) Setup/Hold and High/Low Times FIGURE 6. DS90CR484 (Receiver) Setup/Hold and High/Low Times FIGURE 7. DS90CR483 (Transmitter) Propagation Delay - Latency www.national.com (Continued) 8 10091815 10091816 10091827 ...
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... AC Timing Diagrams (Continued) FIGURE 8. DS90CR484 (Receiver) Propagation Delay - Latency FIGURE 9. DS90CR483 (Transmitter) Phase Lock Loop Set Time 10091828 10091819 9 www.national.com ...
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... AC Timing Diagrams FIGURE 10. DS90CR484 (Receiver) Phase Lock Loop Set Time FIGURE 11. DS90CR483 (Transmitter) Power Down Delay FIGURE 12. DS90CR484 (Receiver) Power Down Delay www.national.com (Continued) 10 10091820 10091821 10091822 ...
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AC Timing Diagrams (Continued) C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max TPPOS — Transmitter output pulse position (min and max) RSKM ≥ Cable Skew (type, length) + ...
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LVDS Interface Optional features supported: Pre-emphasis, and Deskew FIGURE 15. 48 Parallel TTL Data Bits Mapped to LVDS Outputs with DC Balance Enabled www.national.com 12 10091804 ...
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LVDS Interface (Continued) Optional feature supported: Pre-emphasis FIGURE 16. 48 Parallel TTL Data Bits Mapped to LVDS Outputs with DC Balance Disabled 13 10091805 www.national.com ...
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... These three en- hancements allow cables 5+ meters in length to be driven depending upon media and clock rate. The DS90CR483/484 chipset may also be used in a non-DC Balance mode. In this mode pre-emphasis is supported. In TABLE 1. Pre-emphasis DC voltage level with (Rpre) Rpre 1MΩ ...
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... Deskew: Deskew is supported in the DC Balance mode only (BAL = high on DS90CR483). The “DESKEW” pin on the receiver when set high will deskew a minimum of LVDS data bit time skew from the ideal strobe location between signals arriving on independent differential pairs (pair-to-pair skew required that the “ ...
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... PLL and are specified for 65 to 112 MHz operation. The devices will directly inter-operate within the scope of the respective datasheets. The DS90CR483/4 sup- ports a wide operating range from 33 to 112 MHz. The PLLSEL pin is used to select an auto-range feature. It shifts between the two ranges (High and Low) in the MHz range ...
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... BERT. The frequency on the graph is the highest frequency without error. Results: The DS90CR483/4 link was error free at 100MHz over 10 meters of 3M cable using pre-emphasis and DC balance mode off. ) pattern the 48 input channels on the transmitter (DS90CR483). The BERT was ...
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... DS90CR483 Pin Description—Channel Link Transmitter Pin Name I/O TxIN I TxOUTP O TxOUTM O TxCLKIN I TxCLKP O TxCLKM PLLSEL I PRE I DS_OPT I BAL GND I PLLV I CC PLLGND I LVDSV I CC LVDSGND I NC Note 11: Inputs default to “low” when left open due to internal pull-down resistor. ...
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... HIGH state. If the cable interconnect (media) are disconnected which results in floating/terminated inputs, the outputs will remain in the last valid state. Note 14: The DS90CR484 is design to automatically detect the DC Balance or non-DC Balance transmitted data from the DS90CR483 and deserialize the LVDS data according to the define bit mapping. ...
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... Pin Diagram www.national.com Transmitter - DS90CR483 - TQFP (TOP VIEW) 20 10091806 ...
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Pin Diagram Receiver - DS90CR484 - TQFP (TOP VIEW) 21 10091807 www.national.com ...
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... Physical Dimensions Order Number DS90CR483VJD and DS90CR484VJD LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or ...