AD9380 Analog Devices, AD9380 Datasheet
AD9380
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AD9380 Summary of contents
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... Pixel clock output frequencies range from 12 MHz to 150 MHz. PLL clock jitter is typically less than 700 ps p-p at 150 MHz. The AD9380 also offers full sync processing for composite sync and sync-on-green (SOG) applications. The AD9380 contains an HDMI 1.1-compatible receiver and supports all HDTV formats (up to 1080p and 720p) and display resolutions up to SXGA (1280 × ...
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... AD9380 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Specifications..................................................................................... 3 Analog Interface Electrical Characteristics............................... 3 Digital Interface Electrical Characteristics ............................... 4 Absolute Maximum Ratings............................................................ 6 Explanation of Test Levels ........................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Design Guide................................................................................... 12 General Description................................................................... 12 Digital Inputs .............................................................................. 12 Analog Input Signal Handling.................................................. 12 HSYNC and VSYNC Inputs ...
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... 700 2.6 VI 0.8 V − − Binary Rev Page AD9380 AD9380KSTZ-150 Min Typ Max Unit 8 Bits ±0.7 +1.8/−1.0 LSB ±1.1 ±2.25 LSB Guaranteed V DD 0.5 V p–p 1.0 V p–p 220 ppm/°C 1 μA 1.25 5 %FS 1.50 7 %FS ...
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... Output drive = high IV Output drive = low IV 75 Rev Page AD9380KSTZ-150 Min Typ Max 3.15 3.3 3.47 1.7 1.8 1.9 1.7 3.3 3.47 1.7 1.8 1.9 330 130 20 1.15 1.4 130 330 AD9380KSTZ-150 Typ Max Min Typ Max 8 8 2.5 0.8 0.8 − 0.1 − 0.1 0.1 0 700 75 700 Unit V ...
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... Typ Max Min Typ 3.15 3.3 3.47 3.15 3.3 1.7 3.3 347 1.7 3.3 1.7 1.8 1.9 1.7 1.8 1.7 1.8 1.9 1.7 1.8 80 100 100 55 88 110 110 130 130 –0.5 +2.0 −0 AD9380 Max Unit 3.47 V 347 V 1.9 V 1.9 V 110 mA 3 175 145 360 ps 6 Clock Period 900 ps 1300 ps 650 ps 1200 ps 850 ps 1250 ps 800 ps 1200 ps +2 ...
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... AD9380 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
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... SOGIN 0 Input for Sync-on-Green Channel 0 SOGIN 1 Input for Sync-on-Green Channel 1 EXTCLK External Clock Input—Shares Pin with COAST COAST PLL COAST Signal Input—Shares Pin with EXTCLK PWRDN Power-Down Control Rev Page AD9380 GND AIN0 73 SOGIN ...
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... AD9380 Pin Type Pin No. OUTPUTS REFERENCES 57 POWER SUPPLY 80, 76, 72, 67, 45, 33 100, 90, 10 59, 56, 54 48, 32, 30 CONTROL 82 83 HDCP AUDIO DATA OUTPUTS DIGITAL VIDEO DATA ...
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... Input coast polarity defaults power-up. This pin is shared with the EXTCLK function, which does not affect coast functionality. For more details on coast, see the Clock Generation section. Rev Page AD9380 ...
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... HSYNC from the filter, or the filtered HSYNC. See the Sync processing block diagram (see Figure 8 for pin connections). Note that besides slicing off SOG, the output from this pin is not processed on the AD9380. VSYNC separation is performed via the sync separator. ...
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... Digital Input Power Supply. DD This supplies power to the digital logic. GND Ground. The ground return for all circuitry on chip recommended that the AD9380 be assembled on a single solid ground plane, with careful attention to ground current paths. 1 The supplies should be sequenced such that V D ...
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... The AD9380 should be located as close as practical to the input connector. Signals should be routed via 75 Ω matched impedance traces to the IC input pins. At the input of the AD9380, the signal should be resistively terminated (75 Ω to the signal ground return) and capacitively coupled to the AD9380 inputs through 47 nF capacitors. These capacitors form part of the dc restoration circuit ...
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... The offset on the AD9380 can be adjusted automatically to a specified target code. Using this option allows the user to set the offset to any value and be assured that all channels with the same value programmed into the target code match ...
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... Considerable care has been taken in the design of the AD9380 clock generation circuit to minimize jitter. The clock jitter of the AD9380 is less than 13% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible. ...
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... Power Management The AD9380 uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, the power-down bit, and the power-down pin to determine the correct power state. There are four power states: full-power, seek mode, auto power-down, and power-down. ...
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... The output data clock signal is created so that its rising edge always occurs between data transitions and can be used to latch the output data externally. There is a pipeline in the AD9380, which must be flushed before valid data becomes available. This means 23 data sets are presented before valid data is available. ...
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... Sync Processing The inputs of the AD9380 sync processing section are combinations of digital HSYNCs and VSYNCs, analog sync-on- green signal, sync-on-Y signal, and an optional external coast signal. From these signals, the AD9380 generates a precise, jitter-free (9% or less at 95 MHz) clock from its PLL; an odd/even field signal ...
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... N × 200 ns. So the digital comparator threshold is 1 μs. Any pulses less than 1 μs are rejected, while any pulses greater than 1 μs pass through. The sync separator on the AD9380 is simply an 8-bit digital counter with a 6 MHz clock. It works independently of the polarity of the composite sync signal. Polarities are determined elsewhere on the chip ...
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... Register 0x21[6]. The regenerated HSYNC (rather than the raw HSYNC/SOGIN signal) for sync processing is controlled by Register 0x21[7]. Use of the filtered HSYNC and regenerated HSYNC is recommended. Figure 10 shows a filtered HSYNC. EQUALIZATION PULSES EXPECTED EDGE FILTER WINDOW Figure 10. Sync Processing Filter Rev Page AD9380 ...
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... This signal alerts the circuitry following the AD9380 which video pixels are displayable. 4:4:4 TO 4:2:2 FILTER FIELD 1 FIELD 0 The AD9380 contains a filter that allows it to convert a signal from YCrCb 4:4:4 to YCrCb 4:2:2 while maintaining the maximum accuracy and fidelity of the original signal. ...
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... Space Converter User's Guide. AUDIO PLL SETUP Data contained in the audio infoframes, among other registers, define for the AD9380 HDMI receiver not only the type of audio, but the sample frequency. It also contains information about the N and CTS values used to re-create the clock. With this information possible to regenerate the audio sampling frequency ...
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... There is a pipeline in the AD9380 that must be flushed before valid data becomes available. This means six data sets are presented before valid data is available. ...
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... SERIAL REGISTER MAP The AD9380 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed to write and read the control registers through the 2-wire serial interface port. Table 12. Control Register Map Hex Read/Write Default Address or Read-Only ...
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... AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0x12 Read/Write [7] 1******* [6] *0****** [5] **1***** [4] ***0**** [3] ****1*** [2] *****0** [1] ******0* [0] *******1 0x13 Read/Write [7:0] 00000000 0x14 Read/Write [7:0] 00000000 0x15 Read [7] 0******* [6] *0****** [5] **0***** [4] ***0**** [3] ****0*** [2] *****0** [1] ******0* 0x16 Read [7] 0******* [6] *0****** [5] **0***** [4] ***0**** [3] ****0*** [2] *****0** ...
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... HSYNC pulse is missing and down for a good HSYNC. Width of the window in which HSYNC pulses are allowed. Sync Filter Window Width SP Sync Filter Enable Enables coast, VSYNC duration, and VSYNC filter to use the regenerated HSYNC rather than the raw HSYNC. Rev Page AD9380 ...
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... AD9380 Hex Read/Write Default Address or Read-Only Bits Value [6] *1****** [5] **0***** [4] ***0**** [3] **** 1*** [2] **** *1** 0x22 Read/Write [7:0] 4 0x23 Read/Write [7:0] 32 0x24 Read/Write [7] 1******* [6] *1****** [5] **1***** [4] ***1**** [3] ****1*** [2:1] *****11* [0] *******0 0x25 Read/Write [7:6] 01****** [5:4] **11**** [3:2] ****00** Register Name Description PLL Sync Filter Enable Enables the PLL to use the filtered HSYNC rather than the raw HSYNC ...
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... S mode Out Mode 01 = right-justified left-justified raw IEC60958 mode Bit Width Sets the desired bit width for right-justified mode. Rev Page AD9380 2 S output and the MCLK out Set to 1 only for Any mis data pins. ...
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... AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0x2F Read [6] *0****** [5] **0***** [4] ***0**** [3] ****0*** [2:0] *****000 0x30 Read [6] *0****** [5] **0***** [4] ***0**** [3:0] ****0000 0x31 Read/Write [7:4] 1001**** [3:0] ****0110 0x32 Read/Write [7] 0******* [6] *0****** [5:0] **001101 0x33 Read/Write [7] 1******* [6] *0****** [5:0] **010101 0x34 Read/Write [7:6] 10****** [5] **0***** [4] ***0**** [3] ****0*** ...
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... CSC coefficient for equation (A1 × (A2 × G OUT (B1 × R OUT (C1 × (C2 × G OUT IN B Test Must be written to 0x20 for proper operation. Rev Page AD9380 ) + (A3 × (B2 × (B3 × (C3 × (A3 × (B2 × (B3 × ...
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... AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0x56 Read/Write [7:0] 00001111 0x57 Read/Write [7] 0******* [6] *0****** [3] ****0*** [2] *****0** 0x58 Read/Write [7] [6:4] [3] [2:0] 0x59 Read/Write [6] [5] [4] [2] [1] [0] 0x5A Read [6:0] 0x5B Read [3] 0x5E Read [7:6] [5: 0x5F Read [7:0] 0x60 Read [7:4] [3:0] 0x61 Read [5:4] [3:0] Register Name Description Test Must be written to 0x0F for proper operation ...
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... Scan Information S [1:0 information overscanned (television underscanned (computer). Colorimetry C [1:0 data SMPTE 170M, ITU601 ITU709. Picture Aspect Ratio M [1:0 data 4: 16:9. Rev Page AD9380 ...
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... AD9380 Hex Read/Write Default Address or Read-Only Bits Value [3:0] 0x83 Read [1:0] 0x84 Read [6:0] 0x85 Read [3:0] 0x86 Read [7:0] 0x87 Read [6:0] 0x88 Read [7:0] 0x89 Read [7:0] 0x8A Read [7:0] 0x8B Read [7:0] 0x8C Read [7:0] 0x8D Read [7:0] 0x8E Read [7:0] 0x8F Read [6:0] 0x90 Read [7:0] 0x91 Read [7:4] Register Name Description Active Format Aspect R [3:0] ...
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... See CEA 861B for description. Description (SPD) Infoframe Version Vender Name Vender name character 1 (VN1) in 7-bit ASCII code. This is the Character 1 first character the company name that appears on the product. VN2 VN2. VN3 VN3. VN4 VN4. VN5 VN5. Rev Page AD9380 ...
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... AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0x9E Read [7:0] 0x9F Read [6:0] 0xA0 Read [7:0] 0xA1 Read [7:0] 0xA2 Read [7:0] 0xA3 Read [7:0] 0xA4 Read [7:0] 0xA5 Read [7:0] 0xA6 Read [7:0] 0xA7 Read [7:0] 0xA8 Read [6:0] 0xA9 Read [7:0] 0xAA Read [7:0] 0xAB Read [7:0] 0xAC Read [7:0] 0xAD Read [7:0] 0xAE ...
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... ISRC2 Packet Byte 0 (ISRC2_PB0)—This is transmitted only when the ISRC continue bit (Register 0xC8, Bit 7) is set to 1. ISRC2_PB1 ISRC2_PB1. ISRC2_PB2 ISRC2_PB2. New Data Flags New data flags (see Register 0x87). ISRC2_PB3 ISRC2_PB3. ISRC2_PB4 ISRC2_PB4. ISRC2_PB5 ISRC2_PB5. ISRC2_PB6 ISRC2_PB6. ISRC2_PB7 ISRC2_PB7. Rev Page AD9380 ...
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... AD9380 Hex Read/Write Default Address or Read-Only Bits Value 0xE5 Read [7:0] 0xE6 Read [7:0] 0xE7 Read [6:0] 0xE8 Read [7:0] 0xE9 Read [7:0] 0xEA Read [7:0] 0xEB Read [7:0] 0xEC Read [7:0] 0xED Read [7:0] 0xEE Read [7:0] Register Name Description ISRC2_PB8 ISRC2_PB8. ISRC2_PB9 ISRC2_PB9. New Data Flags New data flags (see Register 0x87). ...
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... The greater the error, the greater the number of bars produced. The power-up default value of PLLDIV is 1693 (PLLDIVM = 0x69, PLLDIVL = 0xDx) The AD9380 updates the full divide ratio only when the LSBs are changed. Writing to this register by itself does not trigger an update. 0x02—Bits[7:4] PLL Divide Ratio LSBs The four least significant bits of the 12-bit PLL divide ratio PLLDIV ...
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... The power-up default is 0x80. 0x07—Bits[7:0] Blue Channel Gain These bits control the PGA of the blue channel. The AD9380 can accommodate input signals with a full-scale range of between 0.5 V and 1.0 V p-p. Setting the blue gain to 255 corresponds to an input range of 1 blue gain of 0 establishes an input range of 0 ...
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... HSYNC 0 Detection Bit This bit is used to indicate when activity is detected on the HSYNC 0 input pin. If HSYNC is held high or low, activity is not detected. The sync processing block diagram shows where this function is implemented HSYNC 0 not active HSYNC 0 is active. Rev Page AD9380 ...
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... AD9380 0x15—Bit[6] HSYNC 1 Detection Bit This bit is used to indicate when activity is detected on the HSYNC 1 input pin. If HSYNC is held high or low, activity is not detected. The sync processing block diagram shows where this function is implemented HSYNC 1 not active HSYNC 1 is active. 0x15—Bit[5] VSYNC 0 Detection Bit This bit is used to indicate when activity is detected on the VSYNC0 input pin ...
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... HSYNC position. The HSYNC width is divided into four quadrants with Quadrant 1 starting at the HSYNC leading edge plus a sync separator threshold. If the VSYNC leading edge occurs in Quadrant 1 or Quadrant 4, the field is set to 0 and the output VSYNC is placed coincident with Rev Page AD9380 ...
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... An 8-bit register that sets the duration of the HSYNC output pulse. The leading edge of the HSYNC output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9380 then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the HSYNC output, which is also phase-adjusted. The power-up default is 32. 0x24— ...
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... Circuit blocks that continue to be active during power-down include the voltage references, sync processing, sync detection, and the serial register. These blocks facilitate a fast start-up from power-down normal operation power-down mode. The power-up default setting is 0. Rev Page AD9380 2 S output pins in a high output ...
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... AD9380 0x27—Bit[7] Auto Power-Down Enable This bit enables the chip to go into low power mode, or seek mode if no sync inputs are detected auto power-down disabled chip powers down if no sync inputs present. The power-up default setting is 1. 0x27—Bit[6] HDCP A0 Address ...
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... Allows the previous bit to be used to set low frequency mode rather than the internal autodetect. 0x34—Bit[3] Up Conversion Mode 0 = repeat Cb/Cr values interpolate Cb/Cr values. 0x34—Bit[2] CbCr Filter Enable Enables the FIR filter for 4:2:2 CbCr output. Rev Page AD9380 2 C registers are ...
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... AD9380 COLOR SPACE CONVERSION The default power up values for the color space converter coefficients (R0x35 through R0x4C) are set for ATSC RGB to YCbCr conversion. They are completely programmable for other conversions. 0x34—Bit[1] Color Space Converter Enable This bit enables the color space converter disable color space converter ...
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... N (19:16) These are the most significant 4 bits of a 20-bit word used along with the 20-bit CTS term to regenerate the audio clock. 0x80—Bits[AVI] Infoframe Version Rev Page AD9380 Packet Detected AVI infoframe Audio infoframe SPD infoframe MPEG source infoframe ...
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... AD9380 0x81—Bits[6:5] Y [1:0] This register indicates whether data is RGB, 4:4:4, or 4:2:2. Table 28. Y Video Data 00 RGB 01 YCbCr 4:2:2 10 YCbCr 4:4:4 0x81—Bits[4] Active Format Information Present data active format information valid. 0x81—Bits[3:2] Bar Information Table 29. B Bar Type 00 No bar information 01 Horizontal bar information valid ...
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... Abbreviation FCL FCR RCL RCR LFE Rev Page AD9380 Speaker Placement Front left Front center Front right Front center left Front center right Rear left Rear center Rear right Rear center left Rear center right Low frequency effect ...
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... AD9380 Table 39. CA Bit 4 Bit 3 Bit 2 Bit 1 Bit ...
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... These bits define where the samples are in the ISRC track. At least two transmissions of 001 occur at the beginning of the track, while in the middle of the track, continuous transmission of 010 occurs. This is followed by at least two transmissions of 100 near the end of the track. Rev Page AD9380 ...
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... AD9380 0xC9—Bits[7:0] ISRC1 Packet Byte 0 (ISRC1_PB0) 0xCA—Bits[7:0] ISRC1_PB1 0xCB—Bits[7:0] ISRC1_PB2 0xCC—Bits[7:0] ISRC1_PB3 0xCD—Bits[7:0] ISRC1_PB4 0xCE—Bits[7:0] ISRC1_PB5 0xCF—Bits[6:0] New Data Flags See Register 0x87 for a description. 0xD0—Bits[7:0] ISRC1_PB6 0xD1—Bits[7:0] ISRC1_PB7 0xD2—Bits[7:0] ISRC1_PB8 0xD3— ...
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... Data are read from the control registers of the AD9380 in a similar manner. Reading requires two data transfer operations: • The base address must be written with the R/ W bit of the slave address byte low to set up a sequential read operation. • ...
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... AD9380 SERIAL INTERFACE READ/WRITE EXAMPLES Write to one control register: • Start signal • Slave address byte (R/ W bit = low) • Base address byte • Data byte to base address • Stop signal Write to four consecutive control registers: • Start signal • Slave address byte (R/ W bit = low) • ...
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... An example of a current loop is a power plane to AD9380 to digital output trace to digital data receiver to digital ground plane to analog ground plane. PLL Place the PLL loop filter components as close as possible to the FILT pin ...
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... Adding a series resistor of value 50 Ω to 200 Ω can suppress reflections, reduce EMI, and reduce the current spikes inside the AD9380. If series resistors are used, place them as close as possible to the AD9380 pins (although try not to add vias or extra length to the output trace to move the resistors closer). ...
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... COLOR SPACE CONVERTER (CSC) COMMON SETTINGS Table 44. HDTV YCrCb (0 to 255) to RGB (0 to 255) (Default Setting for AD9380) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x0C 0x52 Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x1C 0x54 Register Blue/Cb Coeff 1 Address 0x45 ...
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... AD9380 Table 48. RGB (0 to 255) to HDTV YCrCb (0 to 255) Register Red/Cr Coeff 1 Address 0x35 0x36 Value 0x08 0x2D Register Green/Y Coeff 1 Address 0x3D 0x3E Value 0x03 0x68 Register Blue/Cb Coeff 1 Address 0x45 0x46 Value 0x1E 0x21 Table 49. RGB (0 to 255) to HDTV YCrCb (16 to 235) ...
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... Dimensions shown in millimeters Temperature Range Package Description 0°C to 70°C 100-Lead Low Profile Quad Flat Package (LQFP) 0°C to 70°C 100-Lead Low Profile Quad Flat Package (LQFP) Evaluation Board Rev Page 16.00 BSC 14.00 BSC 0.27 0.22 0.17 AD9380 Package Option ST-100 ST-100 ...
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... NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05688–0–10/05(0) Rev Page ...