AD7002 Analog Devices, AD7002 Datasheet
AD7002
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AD7002 Summary of contents
Page 1
... IF/RF sections necessity for all GSM mobile systems to use the lowest power possible, the device has power-down or sleep options for all sections (transmit, receive and auxiliary). The AD7002 is housed in 44-lead PQFP (Plastic Quad Flatpack). FUNCTIONAL BLOCK DIAGRAM DV DGND ...
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... Q Tx GMSK ROM Power-Down Option 10%; AGND = DGND = SLEEP = Rx SLEEP A MIN MAX 1 AD7002A Units Test Conditions/Comments 12 Bits Rx SLEEP = SLEEP = Volts Biased on V REF 13 MSPS 270.8 kHz RATE 0 541.7 kHz RATE 1 1 LSB typ 0 6 ...
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... V min/V max 30 mA max 18 mA max 15 mA typ max 11 mA typ 2 mA max –3– AD7002 Test Conditions/Comments Guaranteed Monotonic Unloaded Output AUX DACs Have Unbuffered Resistive Outputs Power-Down Is Implemented by Loading All 1s or All 100 100 ...
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... Gain Error This is a measure of the output error between an ideal DAC and the actual device output with all ls loaded after offset error has been adjusted out and is expressed in LSBs. In the AD7002, gain error is specified for the auxiliary section. Gain Matching Between Channels ...
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... This is the rate at which the modulators on the receive channels sample the analog input. Settling Time This is the digital filter settling time in the AD7002 receive section. On initial power-up, or after returning from the sleep mode necessary to wait this amount of time to obtain use- ful data ...
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... AD7002 1 INPUT CLOCK TIMING (AV DD Limit at Parameter T = – + TRANSMIT SECTION TIMING Limit at Parameter T = – + 100 ...
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... MIN MAX Units Description ns min SLEEP to CAL Setup Time ns min CAL Pulse Width ns min RATE, MODE or THREE-STATE ENABLE Setup Time –7– 10%; AGND = DGND = MHz; CLK1 CLK2 10%; AGND = DGND = AD7002 = 13 MHz; AUX CLK ...
Page 8
... Tx CLK can be used to clock out the transmit data from the ASIC or DSP on the rising edge and Tx DATA is clocked into the AD7002 on the falling edge of Tx CLK. When Tx SLEEP is asserted the transmit section is immediately put into sleep mode, disabling Tx CLK and power- ing down the transmit section ...
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... Figure 8. Typical Spectrum Plot of the Transmit Channel When Transmitting Random Data (0 MHz to 1 MHz) 1.27 1.26 1.25 1.24 1.23 1.22 1.21 Figure 10. Typical Plot of the Composite Vector Magnitude –9– AD7002 FREQUENCY – Hz Figure 6. Transmit Filter Group Delay 0 GMSK MASK GMSK SPECTRUM 0 100 200 300 400 500 ...
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... Due to the low pass nature of the receive filters, there is a settling time associated with step input functions. Output data will not be meaningful until all the digital filter taps have been loaded with data samples taken after the step change. Hence the AD7002 digital filters have a settling time of 44.7 s (288 ...
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... FREQUENCY – kHz Figure 14. Digital Filter Frequency Response and Rx SLEEP 1 RATE Data Format Output Word Rate 0 IQ Data I/Q 270.8 kHz 1 IQ Data I/Q 541.7 kHz 0 I Data Q Data 270.8 kHz 1 I Data Q Data 541.7 kHz AD7002 800 900 1000 high). They 2 ...
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... REF Receive Section Digital Interface A flexible serial interface is provided for the AD7002 receive section. Four basic operating modes are available. Table II shows the truth table for the different serial modes available. The MODE pin determines whether the I and Q serial data is made available on two separate pins (MODE 1) or combined onto a single output pin (MODE 0) ...
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... I LSB Q MSB Q LSB t 35 Figure 17. MODE 0 RATE 0 Receive Timing MSB I LSB MSB Q LSB Figure 18. MODE 1 RATE 1 Receive Timing –13– AD7002 LSB Q MSB Q LSB MSB I LSB ...
Page 14
... FLAG) with three-state control. Communication and sleep control of the auxiliary section is totally independent of either the transmit or receive sections. The AD7002 AUX DACs are voltage mode DACs, consisting of R–2R ladder networks (Figure 20 shows AUX DAC1 archi- tecture), constructed from highly stable thin-films resistors and high speed single pole, double throw switches ...
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... MHz TTL compatible crystal CLK Clock output from the AD7002 which can be used to clock in the data for the transmit section DATA Data input for the transmit section, data is clocked on the falling edge of Tx CLK. ...
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... AD7002 PQFP Pin Number Mnemonic Function 19 I/Q (QDATA) This is a dual function digital output. When the device is operating in MODE 0, it indicates whether IDATA or QDATA is present on Rx DATA pin. In MODE 1, QDATA is available at this pin SYNC Synchronization output for framing I and Q data at the receive interface. ...