AD9856 Analog Devices, AD9856 Datasheet
AD9856
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AD9856 Summary of contents
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... Wireless and satellite communications Cellular base stations GENERAL DESCRIPTION The AD9856 integrates a high speed, direct digital synthesizer (DDS), a high performance, high speed, 12-bit digital-to-analog converter (DAC), clock multiplier circuitry, digital filters, and other DSP functions on a single chip to form a complete OUT quadrature digital upconverter device ...
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... Instruction Byte .......................................................................... 27 Serial Interface Port Pin Descriptions ..................................... 28 MSB/LSB Transfers .................................................................... 28 Notes on Serial Port Operation ................................................ 28 Programming/Writing the AD8320/AD8321 Cable Driver Amplifier Gain Control ............................................................. 30 Understanding and Using Pin-Selectable Modulator Profiles ....................................................................................................... 31 Power Dissipation Considerations........................................... 31 AD9856 Evaluation Board ........................................................ 32 Support ........................................................................................ 32 Outline Dimensions ....................................................................... 35 Ordering Guide .......................................................................... 35 Rev Page ...
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... Unit 1 5 200 MHz 5 50 MHz 5 10 MHz 100 MΩ 12 Bits −10 +10 %FS 10 µ A 0.5 LSB 1 LSB 5 pF −85 dBc/Hz −100 dBc/Hz −110 dBc/Hz −0.5 1 dBc 65 dBc 60 dBc 55 dBc 50 dBc 80 dBc 50 dBm dBc ±0.3 dB AD9856 ...
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... AD9856 Parameter TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulse Width High (t Minimum Clock Pulse Width Low (t Maximum Clock Rise/Fall Time Minimum Data Setup Time ( Minimum Data Hold Time ( Maximum Data Valid Time ( Wake-Up Time Minimum RESET Pulse Width High (t ...
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... Rating 150°C VI. Devices are 100% production tested at 25°C and −65°C to +150°C guaranteed by design and characterization testing for 4 V industrial operating temperature range. −40°C to +85°C −0 300° 38°C/W Rev Page AD9856 ...
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... In most cases, optimal performance is achieved with no external connection. For extremely noisy environments, BG REF BYPASS can be bypassed with 0.1 µF capacitor to AGND (Pin 23). DAC REF BYPASS can be bypassed with 0.1 µF capacitor to AVDD (Pin 27 PIN 1 D11 2 IDENTIFIER D10 3 DVDD 4 DGND 5 AD9856 D9 6 TOP VIEW D8 7 (Not to Scale DVDD 10 DGND ...
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... When continuous mode is enabled via the control bus, the TxENABLE pin becomes an I/Q control line. A Logic 1 Continuous Mode on TxENABLE indicates I data is being presented to the AD9856. A Logic 0 on TxENABLE indicates Q data is being presented to the AD9856. Each rising edge of TxENABLE resynchronizes the AD9856 input sampling capability. ...
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... AD9856 TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL MODULATED OUTPUT SPECTRAL PLOTS RBW 10kHz REF LVL VBW 1kHz –25dBm SWT 12.5s 0 –8 –16 –24 –32 –40 –48 –56 –64 –72 –80 START 0Hz 5MHz/ Figure 3. QPSK at 42 MHz and 2.56 MS/sec; 10.24 MHz External Clock with REFCLK Multiplier = 12, CIC = 3, HB3 On, 2× Data ...
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... A –10 –20 –30 1AP –40 –50 –60 –70 –80 –90 –100 STOP 100MHz START 0Hz Rev Page AD9856 RBW 3kHz RF ATT 20dB VBW 3kHz SWT 28s UNIT dB A 1AP 10MHz/ STOP 100MHz Figure 9. 42 MHz CW Output RBW 3kHz ...
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... AD9856 TYPICAL NARROW-BAND SFDR SPECTRAL PLOTS RBW 100Hz REF LVL VBW 100Hz –5dBm SWT 50s 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 70.1MHz 10kHz/ Figure 11. 70.1 MHz Narrow-Band SFDR, 10 MHz External Clock with REFCLK Multiplier = 20× RBW 100Hz ...
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... Figure 17. 16-QAM, 65 MHz, 2.56 MS/sec TRACE 256QAM MEAS TIME 1 CONST 200 M /DIV –1 1.96078437567 –1.3071895838 TRACE MSK1 MEAS TIME 1.5 CONST 300 M /DIV –1.5 –1.9607843757 1.30718958378 1.63398697972 Rev Page AD9856 1.30718958378 Figure 18. 256-QAM, 42 MHz, 6 MS/sec 1.96078437567 Figure 19. GMSK Modulation, 13 MS/sec ...
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... AD9856 POWER CONSUMPTION 1600 +V = +3V S CIC = 2 +25°C 1400 HB3 = OFF 1200 HB3 = ON 1000 800 120 140 160 CLOCK SPEED (MHz) Figure 20. Power Consumption vs. Clock Speed; V 1600 1500 HB3 = OFF 1400 1300 HB3 = ON 1200 CIC RATE Figure 21. Power Consumption vs. CIC Rate; V ...
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... SERIAL CONTROL BUS REGISTER Table 5. Serial Control Bus Register Layout Register AD9856 Register Layout Address Bit 7 Bit 6 (hex) 00 SDO LSB Active First 01 CIC Continuous Gain Mode Interpolator Interpolator Rate <5> Rate <4> Interpolator Interpolator Rate <5> Rate <4> ...
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... The AD9856 dedicates three output pins, which directly interface to the AD8320/AD8321 cable driver amp. This allows direct control of the cable driver via the AD9856. See the Error! Reference source not found. section for more details. Bit 7 is the MSB, Bit 0 is the LSB. Default value is 00h. ...
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... Rather, the user’s baseband data is required to be upsampled by at least a factor of two (2) before being applied to the AD9856 in order to minimize the frequency-dependent attenuation associated with the CIC filter stage (see the Cascaded Integrator Comb (CIC) Filter section ) ...
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... The quarter-word mode accepts multiple 3-bit I and Q data inputs to form a 12-bit word. For all word length modes, the AD9856 assembles the data for signal processing into time-aligned, parallel, 12-bit I/Q pairs. In addition to the word length flexibility, the AD9856 has two input timing modes, burst or continuous, that are programmable via the serial port ...
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... As in burst mode, the rising edge of TxENABLE synchronizes the AD9856 to the input data rate and the data is registered at the approximate center of the data-valid time. The continuous operating mode can only be used in conjunction with the full- word input format ...
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... AD9856 TxENABLE D(11:0) I0 INTERNAL I INTERNAL Q TxENABLE D(11:0) I0 INTERNAL I INTERNAL Q TxENABLE I0(11:6) D(11:6) INTERNAL I INTERNAL Q TxENABLE I0(11:9) D(11:9) INTERNAL I INTERNAL Q TxENABLE D(11:0) IN INTERNAL I IN–2 INTERNAL Q QN– Figure 24. 12-Bit Input Mode, Classic Burst Timing Figure 25. 12-Bit Input Mode, Alternate TxENABLE Timing ...
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... Continuous Mode Input Timing The AD9856 is configured for continuous mode input timing by writing the continuous mode bit true (Logic 1). The continuous mode bit is in register address 01h, Bit 6. The AD9856 must be configured for full-word input format when operating in continuous mode input timing. The input data rate equations described previously for full-word mode apply for continuous mode ...
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... HBF 1 and HBF 2. Furthermore, if the baseband data applied to the AD9856 has been pulse shaped, there is an additional concern. Typically, pulse shaping is applied to the baseband data via a filter having a raised cosine response. In such cases, an α ...
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... The alternate form yields an indeterminate form (0/0) for but is otherwise identical. The only variable parameter for the AD9856 CIC filter and N are fixed at 1 and 4, respectively. Thus, the CIC system function for the AD9856 simplifies to: ...
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... Another issue to consider with the CIC filters is insertion loss. Unfortunately, CIC insertion loss is not fixed, but is a function and N. Because M, and N are fixed for the AD9856, the CIC insertion loss is a function of R only. Interpolation rates that are an integer power-of-2 result in no insertion loss ...
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... Direct Digital Synthesizer Function section) with the appropriate 32-bit tuning word via the AD9856 control registers. The DDS simultaneously generates a digital (sampled) sine and cosine wave at the programmed carrier frequency. The ...
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... SINC envelope distortion. 1.0517 0.437 This can be accomplished by means of an ISF. The ISF 1.1305 1.065 incorporated on the AD9856 is a 17-tap, linear phase FIR filter. 1.2132 1.679 Its frequency response characteristic is the inverse of the SINC 1.2998 2.278 envelope ...
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... SINC and ISF responses). Note that the ISF exhibits an insertion loss of 3.1 dB. Thus, signal levels at the output of the AD9856 with the ISF bypassed are 3.1 dB higher than with the ISF engaged. For modulated output signals, however, which have a relatively wide bandwidth, the benefits of the SINC compensation usually outweigh the 3 dB loss in output level ...
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... With the REFCLK multiplier enabled, the input reference clock required for the AD9856 can be kept in the 10 MHz to 50 MHz range for 200 MHz system operation, which results in cost and system implementation savings. The REFCLK mult- iplier function maintains clock integrity as evidenced by the AD9856’ ...
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... SCLK edges to be the instruction byte of the next communication cycle. All data input to the AD9856 is registered on the rising edge of SCLK. All data is driven out of the AD9856 on the falling edge of SCLK. Figure 44 through Figure 47 show the general operation of the AD9856 serial port. ...
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... AD9856, the SYNC I/O pin provides a means to reestablish synchronization without reinitializing the entire chip. The SYNC I/O pin enables the user to reset the AD9856 state machine to accept the next eight SCLK rising edges to be coincident with the instruction phase of a new communication cycle ...
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... SERIAL DATA SETUP TIME DSU t SERIAL DATA CLOCK PULSEWIDTH HIGH SCLKPWH t SERIAL DATA CLOCK PULSEWIDTH LOW SCLKPWL t SERIAL DATA HOLD TIME DHLD Figure 48. Timing Diagram for Data Write to AD9856 CS SCLK SDIO 1ST BIT SDO t SYMBOL DEFINITION t DATA VALID TIME DV Figure 49. Timing Diagram for Read from AD9856 Rev ...
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... AD9856 gain control register is updated. The user does not have to write the AD9856 in any particular order concerned with time between writes. If the AD9856 is currently writing to the AD8320/AD8321 while one of the four AD9856 gain control registers is being addressed, the AD9856 ...
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... MAX dissipation by nearly 25%. For the first method, the input data must be externally 4× upsampled. The AD9856 must be configured for a CIC interpolation rate of three while bypassing the 3rd half-band filter. This results in an I/Q input sample rate of 24 MHz which is further upsampled by a factor of 8 MHz to 192 MHz. ...
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... In this power reduction technique, the larger the REFCLK multiplier factor, the larger the power savings. The AD9856 is specified for operation at +3.0 V ±5%. The thermal impedance of the device in the 48-LQFP plastic package is 38°C/W. At 200 MHz operation, power dissipation is 1 ...
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... RBE 30 GND 31 SDO 32 33 +3.3V 34 C31 C29 C24 C30 36 10µ F 0.1µ F 0.1µ F 0.1µ F 0.1µ F 10µ F Figure 51. AD9856/PCB Evaluation Board Electrical Schematic SYNC I/O J8 SCLK J4 SDIO J15 SDO J14 GND E5 E8 CACLK ...
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... Figure 53. PCB Lay Out Pattern for Four-Layer AD9856 PCB Evaluation Board Layer 2—Ground Plane REF CLOCK IN Figure 56. Basic Implementation of AD9856 Digital Modulator and AD8320/AD8321 Programmable Cable Driver Amplifier Figure 54. PCB Lay Out Pattern for Four-Layer AD9856 PCB Evaluation Board Figure 55. PCB Lay Out Pattern for Four-Layer AD9856 PCB Evaluation Board ...
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... Figure 58. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in inches millimeters Package Description 48-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board Rev Page 9.00 BSC PIN 1 TOP VIEW 7.00 BSC SQ (PINS DOWN 0.27 0.50 BSC 0.22 0.17 Package Option ST-48 AD9856 ...
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... AD9856 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00637–0–1/05(C) Rev Page ...