AD71028 Analog Devices, AD71028 Datasheet
AD71028
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AD71028 Summary of contents
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... The output of the AD71028 can be connected with minimal external circuitry to the input of a 4.5 MHz aural FM modulator. In addition to the BTSC encoders, the AD71028 also includes a stereo image enhancement function, Phat Stereo, to increase the sense of spaciousness available from closely spaced TV loudspeakers. A dialog enhancement algorithm is also included to solve the problem of playing wide dynamic range sources over limited-performance TV speakers and amplifiers ...
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... AD71028 TABLE OF CONTENTS Specifications..................................................................................... 3 DAC Analog Performance........................................................... 3 BTSC Encoder Performance ....................................................... 3 Digital I/O ..................................................................................... 3 Power.............................................................................................. 4 Temperature Range ...................................................................... 4 Digital Timing............................................................................... 4 Absolute Maximum Ratings............................................................ 5 Pin Configuration and Functional Descriptions.......................... 6 Features .............................................................................................. 8 Pin Functions ................................................................................ 8 Signal Processing ............................................................................ 10 Background of BTSC ................................................................. 10 Performance Factors .................................................................. 10 Separation Alignment ................................................................ 10 Phase Linearity of the External Analog Filter......................... 11 ...
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... kHz 24 Bits 50 pF 2.4 V 0.4 V Min +0.5 +0.5 Min 2.1 DVDD – 0.5 Rev Page Min Typ –85 –92 1.7 Typ Max Unit –1.0 dB –1.5 dB Typ Max 0 0.4 AD71028 Max Unit Bits p-p Unit V V µA µ ...
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... AD71028 POWER Table 4. Parameter Supplies Voltage, Analog and Digital Analog Current Digital Current Dissipation Operation—Both Supplies Operation—Analog Supplies Operation—Digital Supplies TEMPERATURE RANGE Table 5. Parameter Specifications Guaranteed Functionality Guaranteed Storage DIGITAL TIMING Table 6. Parameter t MCLK Recommended Duty Cycle @ 12.288 MHz (256 × f ...
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... ABSOLUTE MAXIMUM RATINGS Table 7. AD71028 Stress Ratings Parameter Min DV to DGND –0.3 DD ODV to DGND –0.3 DD AVDD to AGND –0.3 Digital Inputs DGND – 0.3 Analog Inputs AGND – 0.3 AGND to DGND –0.3 Reference Voltage Maximum Junction Temperature Storage Temperature Range –65 Soldering ESD CAUTION ESD (electrostatic discharge) sensitive device ...
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... OUTB+ 35 OUTB– 37 REFCAP 38 FILTCAP DIV2_PA 1 DIV1_PB 2 DIV2_PB AD71028 DGND 6 TOP VIEW DVDD 7 (Not to Scale) ODVDD COUT 11 CDATA CONNECT Figure 2. 48-Lead Low Profile Quad Flat Pack (LQFP) ...
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... Input for 27 MHz Video Reference Clock, Processor B IN Input from External PLL, Processor A IN Clock Input to Processor A IN Input from External PLL, Processor B IN Clock Input to Processor B OUT PLL_PA Clock (Pin 42) Divided by 512 (DOUBLE = 1) or 1024 (DOUBLE = 0) Rev Page AD71028 ...
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... The AD71028 accepts serial audio data in MSB first, twos complement format. The AD71028 operates from a single 5 V power supply fab- ricated on a single monolithic integrated circuit and is housed in a 48-lead LQFP package for operation over the 0°C to 70°C temperature range ...
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... This level may be adjusted by writing to SPI location 258. OUTB+, OUTB– Differential analog outputs for Processor B. The nominal output voltage for a 1 kHz 0 dB mono input signal is 600 mV rms. This level may be adjusted by writing to SPI location 770. Rev Page AD71028 ...
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... SEPARATION ALIGNMENT The BTSC encoder outputs are all specified in terms of the deviation of the FM 4.5 MHz carrier. For the AD71028, a digital input level (mono signal) should cause a carrier deviation of ±25 kHz without the 75 µs pre-emphasis filter. In practice, the pre-emphasis filter may be left in for this adjust- ment, as long as the frequency is low enough to not be affected by the pre-emphasis filter ...
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... This pin should be tied either high or low and should not be changed after power-up. The AD71028 requires a master clock at either 256 × 48 kHz (12.288 MHz) when DOUBLE = 1 or 512 × 48 kHz (24.576 MHz) when DOUBLE = 0. In some cases, this signal is provided by the MPEG decoder chip itself ...
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... CDATA HI-Z COUT OVERVIEW The AD71028 can be controlled using the SPI port. In general, there are three parameters per processor that can be controlled: the encoder output level, the Phat Stereo image enhancement algorithm, and the dialog enhancement algorithm also possible to write new data into the parameter RAM to alter the filter coefficients used in the BTSC encoding process ...
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... This gain value should range from 0 (–∞ dB) to +2.0 – 1 LSB (approximately +6 dB). The gain at a –87 dB input corresponds to parameter RAM location 4 on Processor A and location 516 on Processor B. The table extends to the +9 dB input gain at locations 36 and 548 for Processors A and B, respectively. Rev Page AD71028 ...
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... SPI registers during this period of time. SERIAL DATA INPUT PORT The AD71028’s flexible serial data input port accepts data in twos complement, MSB-first format. The left channel data field always precedes the right channel data field. The serial mode is set by using mode select bits in the SPI control register ...
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... S Mode—16 Bits to 24 Bits per Channel LSB Figure 9. Right-Justified Mode—16 Bits to 24 Bits per Channel MSB LSB Figure 10. DSP Mode—16 Bits to 24 Bits per Channel . S Rev Page AD71028 RIGHT CHANNEL LSB RIGHT CHANNEL LSB RIGHT CHANNEL MSB LSB LSB ...
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... All current sources are derived from the VREF input pin. The gain of the AD71028 is directly proportional to the magnitude of the current sources, and therefore the gain of the AD71028 is proportional to the voltage on the VREF pin. The nominal VREF voltage should be set to 2.5 V, using a simple resistive divider from the analog supply ...
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... COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 13. 48-Lead Low Profile Quad Flatpack [LQFP] (ST-48) Dimensions Shown in Millimeters Package Description 48-Lead LQFP 48-Lead LQFP Rev Page 9.00 BSC PIN 1 TOP VIEW 7.00 BSC SQ (PINS DOWN 0.27 0.50 0.22 BSC 0.17 Package Option ST-48 ST-48 on 13” Reel AD71028 ...
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... AD71028 NOTES Rev Page ...
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... NOTES Rev Page AD71028 ...
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... AD71028 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04482–0–1/04(0) Rev Page ...