ADV7172 Analog Devices, ADV7172 Datasheet
ADV7172
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ADV7172 Summary of contents
Page 1
... A PC’98-Compliant autodetect feature has been added to allow the user to determine whether or not the DACs are correctly terminated. If not, the ADV7172/ ADV7173 flags that they are not connected through the Status bit and provides the option of automatically powering them down, thereby reducing power consumption ...
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... REAL-TIME CONTROL CIRCUIT GND SCRESET/RTC input data from 1 to 254 on both Y, Cb, and Cr. The ADV7172/ ADV7173 supports PAL ( and NTSC (with and without pedestal) standards. The Y data is then manipulated by being scaled for contrast control and a setup level is added for brightness control. The Cr, Cb data is also scaled and saturation control is added ...
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... R SET2 L = 1041 Ω 262.5 Ω R SET2 OUT = 20 µA I VREFOUT = 600 Ω R SET1,2 = 1041 Ω R SET1,2 = 150 Ω R SET1 COMP = 0.1 µF ADV7172/ADV7173 to T MIN MAX Min Typ Max Unit 10 Bits ± 1.0 LSB ± 1.0 LSB 2 V 0.8 V ± 1 µ 2.4 V 0.4 V µA ...
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... ADV7172/ADV7173–SPECIFICATIONS (V AA 3.3 V SPECIFICATIONS unless otherwise noted.) Parameter 3 STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity 3 DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance DIGITAL OUTPUTS Output High Voltage, V ...
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... REF 2 specifications unless otherwise noted.) MIN MAX 1 Conditions Normal Power Mode Normal Power Mode Lower Power Mode Lower Power Mode RMS Peak Periodic RMS Peak Periodic Referenced to 40 IRE ADV7172/ADV7173 = 600 unless otherwise noted. All Min Typ Max Unit 0.3 0.7 % 0.4 0.7 Degrees 0.5 1.0 % 2.0 3.0 ...
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... ADV7172/ADV7173 5 V TIMING SPECIFICATIONS Parameter 3, 4 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time SDATA, SCLOCK Fall Time, t ...
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... TTX Specifications subject to change without notice 3.0 V–3 1.235 REF otherwise noted.) Conditions After this period the 1st clock is generated relevant for repeated Start Condition. ADV7172/ADV7173 = 600 . All specifications SET1,2 MIN MAX Min Typ Max Unit 0 400 kHz µ ...
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... DAC normal power mode the average current consumed by each DAC is the DAC output current as determined by R (see Appendix 8). In Low Power Mode the average current consumed by each DAC is approximately half the DAC output current as determined by R Consult AN-551 for detailed information on ADV7172/ADV7173 power management ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7172/ADV7173 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Dual Function CSO or HSO TTL Output Sync Signal. TTL Address Input. This signal sets up the LSB of the MPU address. The input resets the on-chip timing generator and sets the ADV7172/ADV7173 into default mode. This is NTSC operation, Timing Slave Mode 0, DACs A, B, and C powered OFF, DACs D, E, and F powered ON, Composite and S-Video out ...
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... MONOTONIC 0. MONOTONIC 1 0.0645 2 0.084 0 MONOTONIC 0 ADV7172/ADV7173 STOPBAND STOPBAND CUTOFF (MHz) ATTENUATION (dB) 7.37 –56 7.96 –64 8.3 –68 8.0 –66 8.0 –61 7.06 –61 7.15 –50 STOPBAND STOPBAND CUTOFF (MHz) ATTENUATION (dB) 3.01 –45 3.64 –58.5 3.73 –49 5.0 –40 3.01 –45 4.08 –50 0 –10 – ...
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... ADV7172/ADV7173 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 – ...
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... ADV7172/ADV7173 FREQUENCY – MHz FREQUENCY – MHz FREQUENCY – MHz ...
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... PAL. These are enabled by setting MR46 of Mode Register 4 to Logic “1.” SQUARE PIXEL MODE The ADV7172/ADV7173 can be used to operate in square pixel mode. For NTSC operation, an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accord- ingly for square pixel mode operation ...
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... REAL-TIME CONTROL Together with the SCRESET/RTC PIN and Bits MR42 and MR41 of Mode Register 4, the ADV7172/ADV7173 can be used to lock to an external video source. The real-time control mode allows the ADV7172/ADV7173 to automatically alter the subcarrier frequency to compensate for line length variation. ...
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... Mode 0 (CCIR–656): Slave Option (Timing Register 0 TR0 = The ADV7172/ADV7173 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace ...
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... Register 0 TR0 = The ADV7172/ADV7173 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the FIELD/VSYNC pin ...
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... In this mode the ADV7172/ADV7173 accepts horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is dis- abled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). ...
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... HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illus- trates the HSYNC, BLANK, and FIELD for an odd-or-even field transition relative to the pixel data ...
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... Register 0 TR0 = this mode the ADV7172/ADV7173 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. ...
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... HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 30 (NTSC) and Figure 31 (PAL). Figure 32 illustrates the HSYNC, BLANK, and VSYNC for an even-to-odd field transition relative to the pixel data ...
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... In this mode the ADV7172/ADV7173 accepts or generates horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7172/ADV7173 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 34 (NTSC) and Figure 35 (PAL). ...
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... SCH phase jumps at the start of the four or eight field sequence. Resetting the SCH phase should not be done if the video source does not have stable timing or the ADV7172/ADV7173 is con- figured in RTC mode (MR41 = “1” and MR42 = “1”). Under these conditions (unstable video) the subcarrier phase reset should be enabled (MR42 = “ ...
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... The LSB sets either a read or write operation. Logic Level “1” corresponds to a read operation while Logic Level “0” corresponds to a write operation set by setting the ALSB pin of the ADV7172/ADV7173 to Logic Level “0” or Logic Level “1.” When ALSB is set to “0,” there is greater bandwidth 2 ...
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... The ADV7172/ADV7173 acts as a standard slave device on the bus. The data on the SDATA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting sub- address. The subaddresses auto increment allows data to be written to or read from the starting subaddress ...
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... MACROVISION REGISTER [ADV7172 ONLY MACROVISION REGISTER [ADV7172 ONLY MACROVISION REGISTER [ADV7172 ONLY MACROVISION REGISTER [ADV7172 ONLY MACROVISION REGISTER [ADV7172 ONLY MACROVISION REGISTER [ADV7172 ONLY MACROVISION REGISTER [ADV7172 ONLY] ...
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... Figure 44 shows the various operations under the control of Mode Register 0. MR0 BIT DESCRIPTION Output Video Standard Selection (MR01–MR00) These bits are used to set up the encoder mode. The ADV7172/ ADV7173 can be set up to output NTSC, PAL ( I), PAL M or PAL N standard video. Luma Filter Select (MR02–MR04) These bits specify which luma filter selected ...
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... When this bit is set (“1”), sleep mode is enabled. With this mode enabled the ADV7172/ADV7173 power consumption is reduced to less than 20 µA. The I and read from when the ADV7172/ADV7173 is in sleep mode. If “0” is written to MR27 when the device is in sleep mode, the ADV7172/ADV7173 will come out of sleep mode and resume normal operation ...
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... MODE CONTROL MR32 MR34 DISABLE 1 ENABLE CLOSED CAPTIONING TELETEXT FIELD SELECTION ENABLE MR35 MR33 0 NO DATA OUT 0 DISABLE 1 ODD FIELD ONLY 1 ENABLE 0 EVEN FIELD ONLY 1 DATA OUT (BOTH FIELDS) ADV7172/ADV7173 MR32 MR31 MR30 MR31 MR30 DISABLE RESERVED FOR REVISION CODE ENABLE ...
Page 30
... Field 0 whenever a low-to-high field transition is detected on the SCRESET/RTC pin MR42 is set to “1,” the SCRESET/RTC pin is configured as a real-time control input and the ADV7172/ADV7173 can be used to lock to an external video source. MR47 COLOR BAR ...
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... Betacam levels when configured in PAL mode and SMPTE levels when configured in NTSC mode. UV-Levels Control (MR52–MR51) These bits control the U and V output levels on the ADV7172/ ADV7173 possible to have UV levels with a peak-peak amplitude of either 700 mV (MR52 + MR51 = “01”) or 1000 mV (MR52 + MR51 = “ ...
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... Composite DAC Status Bit (MR67) This bit is a read only status bit for the autodetect feature of the ADV7172/ADV7173 and may be read to check whether or not the luma DAC is terminated. If this bit is set (“1”), there is no termination. If this bit is set (“0”), the luma DAC is terminated. ...
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... THESE BITS MR77 MR76 Brightness Enable Control (MR73) This bit is used to enable brightness control on the ADV7172/ ADV7173 by enabling the programmable “setup level” or ped- estal described in the Brightness Control Register to be added to the scaled Y data. When this bit is set (“1”), brightness control is enabled. When this bit is set (“ ...
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... Min Luma Value (TR06) The bit is used to control the minimum luma value output by the ADV7172/ADV7173. When this bit is set to (“1”), the luma is limited to 7.5 IRE below the blank level. When this bit is set to (“0”), the luma value can be as low as the sync bottom level. ...
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... TIMING MODE 1 (MASTER/PAL) HSYNC FIELD/VSYNC HSYNC to FIELD Rising Edge Delay (TR15–TR14) When the ADV7172/ADV7173 is in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the FIELD output rising edge. VSYNC Width (TR15–TR14) When the ADV7172/ADV7173 is configured in Timing Mode 2, these bits adjust the VSYNC pulsewidth. HSYNC to Pixel Data Adjust (TR17– ...
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... ADV7172/ADV7173 SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC3–FSC0) (Address (SR4–SR0) = 0CH–0FH) These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following equation: Subcarrier Frequency Re gister Example: NTSC Mode MHz, CLK f = 3.5795454 MHz ...
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... When this bit is enabled (“1”), the last six bits of the CGMS data, i.e., the CRC check sequence, are calculated internally by the ADV7172/ADV7173. If this bit is disabled (“0”), the CRC values in the register are output to the CGMS data stream. CGMS Odd Field Control (C/W05) When this bit is set (“ ...
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... ADV7172/ADV7173 CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10) (Address (SR4–SR0) = 1AH) CGMS_WSS Register 8-bit-wide register. Figure 61 shows the operations under control of this register. C/W1 BIT DESCRIPTION CGMS/WSS Data (C/W15–C/W10) These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data. CGMS Data Only (C/W17– ...
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... The ADV7172/ADV7173 provides a range of ± 22° in incre- ments of 0.17578125°. For normal operation (zero adjustment) this register is set to 80 Hex. FFHex and 00Hex represent the upper and lower limit (respectively) of adjustment attainable. Hue Adjust = (0.17568125 × ...
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... ADV7172/ADV7173 BRIGHTNESS CONTROL REGISTERS (BCR) (Address (SR5–SR0) = 21H) The brightness control register is an 8-bit-wide register which allows brightness control. Figure 66 shows the operation under control of this register. BCR BIT DESCRIPTION Reserved (BCR7–BCR5) A Logic “0” must be written to these bits. ...
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... The Recommended Analog Circuit Layout shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7172/ ADV7173 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups ...
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... FOR EACH POWER SUPPLY GROUP 0 0 11, 19, 27, 30, 32, 34 COMP1 AA DAC COMP2 37 V REF DAC ADV7172/ ADV7173 9 P7 CSO_HSO DAC VSO 45 42 CLAMP DAC D 28 PAL_NTSC 43 39 SCRESET/RTC 25 DAC E HSYNC 14 15 FIELD/VSYNC BLANK ...
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... FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. The ADV7172/ADV7173 uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data, unlike other 2-byte deep buffering systems ...
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... Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is output on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7172/ADV7173 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a refer- ence pulse of the same amplitude and duration as a CGMS bit (see Figure 70) ...
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... The ADV7172/ADV7173 supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7172/ADV7173 is configured in PAL mode. The WSS data is 14 bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code (see Figure 71). ...
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... Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7172/ADV7173 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal that can be outputted on the CVBS and Y outputs. ...
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... BLACK LEVEL BLANK LEVEL SYNC LEVEL REF WHITE 714.2mV BLACK LEVEL BLANK LEVEL SYNC LEVEL 629.7mV (p-p) REF WHITE 720.8mV BLACK LEVEL BLANK LEVEL SYNC LEVEL ADV7172/ADV7173 1268.1mV 1048.4mV 387.6mV 334.2mV 48.3mV 1048.4mV 387.6mV 334.2mV 48.3mV PEAK CHROMA BLANK/BLACK LEVEL PEAK CHROMA 1052.2mV 387 ...
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... ADV7172/ADV7173 130.8 IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 978mV 286mV (p-p) 650mV 299.3mV 0mV 100 IRE 0 IRE –40 IRE NTSC WAVEFORMS (WITHOUT PEDESTAL) PEAK COMPOSITE 1289.8mV REF WHITE 1052.2mV 714.2mV BLANK/BLACK LEVEL 338mV SYNC LEVEL 52.1mV 1052.2mV REF WHITE 714 ...
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... ADV7172/ADV7173 PEAK COMPOSITE REF WHITE 696.4mV BLANK/BLACK LEVEL SYNC LEVEL REF WHITE 696.4mV BLANK/BLACK LEVEL SYNC LEVEL PEAK CHROMA 672mV (p-p) BLANK/BLACK LEVEL PEAK CHROMA REF WHITE 698 ...
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... ADV7172/ADV7173 334mV 171mV BETACAM LEVEL 0mV 171mV 334mV 505mV 309mV 158mV BETACAM LEVEL 0mV –158mV –309mV –467mV 232mV SMPTE LEVEL 118mV 0mV –118mV –232mV –350mV UV WAVEFORMS 505mV BETACAM LEVEL 0mV 467mV BETACAM LEVEL 0mV 350mV SMPTE LEVEL 0mV 505mV 423mV 82mV 0mV – ...
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... DAC outputs, the configuration in Figure 94 is recommended. This configuration shows the DAC outputs running at half (18 mA) their full current (36 mA) capability. This will allow the ADV7172/ADV7173 to dissipate less power; the analog current is reduced by 50% with a R SET1 600 Ω and Ω ...
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... ADV7172/ADV7173 The ADV7172/ADV7173 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. In each case the output is set to composite/luma/chroma outputs with DACs D, E and F powered up to provide 8.66 mA and with the BLANK input control disabled. Additionally, the burst and color information are enabled on the output and the inter- nal color bar generator is switched off ...
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... Color Control Register 1 00Hex 1FHex Color Control Register 2 00Hex 20Hex Hue Control Register 00Hex 21Hex Brightness Control Register 00Hex 22Hex Sharpness Control Register 00Hex ADV7172/ADV7173 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex Data 12Hex 07Hex 68Hex 00Hex 00Hex ...
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... ADV7172/ADV7173 POWER ON RESET REG VALUES (PAL_NTSC = 0, NTSC Selected) Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode Register 7 0AHex Timing Register 0 0BHex Timing Register 1 0CHex Subcarrier Frequency Register 0 ...
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... SLOW CLAMP TO 0. 6.72 s 0.5 0.0 L575 0.0 10.0 20.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0. 6.72 s APPENDIX 10 30.0 40.0 50.0 MICROSECONDS PRECISION MODE OFF SOUND-IN-SYNC OFF SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED 30.0 40.0 50.0 60.0 MICROSECONDS PRECISION MODE OFF SOUND-IN-SYNC OFF SYNCHRONOUS SYNC = A FRAMES SELECTED: 1 ADV7172/ADV7173 60.0 70.0 ...
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... ADV7172/ADV7173 0.5 0.0 –0.5 L575 10.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW CLAMP TO 0. 6.72 s 100.0 0.5 50.0 0.0 0.0 –50.0 0.0 APL = 44.6% 525 LINE NTSC SLOW CLAMP TO 0. 6.72 s 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING SYNCHRONOUS F1 L76 10.0 20.0 30.0 40.0 MICROSECONDS PRECISION MODE OFF NO FILTERING 50.0 60.0 NO BRUCH SIGNAL SOUND-IN-SYNC OFF ...
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... LINE NTSC NO FILTERING SLOW CLAMP TO 0. 6.72 s 0.4 50.0 0.2 0.0 –0.2 –50.0 –0.4 F1 L76 0.0 10.0 20.0 NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0. 6.72 s ADV7172/ADV7173 30.0 40.0 50.0 MICROSECONDS SYNCHRONOUS SYNC = SOURCE FRAMES SELECTED 30.0 40.0 50.0 60.0 MICROSECONDS PRECISION MODE OFF SYNCHRONOUS SYNC = B FRAMES SELECTED 60.0 ...
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... ADV7172/ADV7173 APL = 39. SOUND IN SYNC OFF APL = 45.1% YI –Q SETUP 7. 75% 100 R 100% 75 SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V & – SYSTEM LINE L76F1 ANGLE (DEG) 0 ...
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... Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC 0.057 (1.45) 0.030 (0.75) 0.276 (7.0) BSC 0.030 (0.75) 0.053 (1.35) 0.018 (0.45) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN) 0.006 (0.15 0.002 (0.05) 0° MIN 0° – 7° 0.007 (0.18) 0.019 (0.5) 0.011 (0.27) 0.004 (0.09) BSC 0.006 (0.17) ADV7172/ADV7173 ...
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