AD9803 Analog Devices, AD9803 Datasheet
AD9803
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AD9803 Summary of contents
Page 1
... The AUX input features a wideband PGA and input clamp, and can be used to sample analog video signals. The AD9803 nominally operates from a single 3 V power sup- ply, typically dissipating 170 mW. The AD9803 is packaged in a space-saving 48-lead LQFP and is specified over an operating temperature range of – ...
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... AD9803–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE (For Functional Operation) Analog Digital Digital Driver POWER CONSUMPTION (Power-Down Modes Selected Through Serial I/F) Normal Operation (D-Reg 00) High Speed AUX-MODE (D-Reg 01) Reference Standby (D-Reg 10 or STBY Pin Hi) Shutdown Mode (D-Reg 11) ...
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... ACVDD = ADVDD = DVDD = +2 MIN MAX noted) Min 18 1000 1000 1000 –3 MAX INPUT SIGNAL W/PBLK ENABLED –3– AD9803 = MHz unless otherwise SHP SHD ADCCLK Typ Max Units 150 mW 170 mW 185 mW MHz 0 dB 500 mV mV p-p mV p-p mV p-p ...
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... AD9803–SPECIFICATIONS AUX-MODE SPECIFICATIONS Parameter POWER CONSUMPTION Normal (D-Reg 00) High Speed (D-Reg 01) MAXIMUM CLOCK RATE PGA Max Input Range Max Output Range Digital Gain Control Gain Control Resolution Gain (Selected by the Serial I/F) Gain(0) Gain(255) ACTIVE CLAMP (CLAMP ON) Clamp Level (Selectable by the Serial I/F) ...
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... N–6 Figure 1. CCD-MODE Timing N+1 N+2 N N–3 N–2 NOTE: EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE. Figure 2. AUX-MODE and ADC-MODE Timing BLANKING OPTICAL BLACK INTERVAL Figure 3. CCD-MODE Clamp Timing –5– AD9803 N+3 N+4 N–5 N–4 N– INHIBIT N+5 N+4 N–1 N EFFECTIVE DUMMY BLACK PIXELS ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9803 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... DAC1 Output DAC2 Output Serial I/F Load Signal Serial I/F Clock Analog Supply (3 V) Serial I/F Input Data Analog Ground Analog Ground Bottom Reference (0 Ground and VRT) Top Reference (0 Ground) –7– AD9803 ADCIN 36 35 AUXCONT AUXIN 34 33 ACVDD 32 CLPBYP ACVSS ...
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... AD9803 EQUIVALENT INPUT CIRCUITS DVDD DVSS Figure 5. Pins 2–11 (D0–D9) DVDD 200 DVSS Figure 6. Pin 16, 21, 22 (ADCCLK, SHP, SHD) ACVDD 50 SUBST ACVSS Figure 7. Pins 25, 28 (CCDBYP) DRVDD SUBST DRVSS Figure 8. Pin 26 (DIN) and Pin 27 (PIN) PGACONT1 PGACONT2 DVSS Figure 9. Pin 29 (PGACONT1) and Pin 30 (PGACONT2) SUBST – ...
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... ADVDD 1.4pF INTERNAL DAC OUT 39k 39k ADVSS Figure 14. Pin 39 (DAC1) and 40 (DAC2) DATA OUT RNW Figure 15. Pin 44 (SDATA) 3k ADVDD 200 SUBST ADVSS Figure 16. Pin 47 (VRB) and Pin 48 (VRT) –9– AD9803 70 DAC1, DAC2 OUTPUT DVDD DRVDD SDATA DATA IN DVSS DRVSS 1.1k ...
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... AD9803 –Typical Performance Characteristics 240 220 V = 3.3V DD 200 V = 3.0V DD 180 V = 2.8V DD 160 140 120 SAMPLE RATE – MHz Figure 17. CCD-MODE Power vs. Clock Rate 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 0 150 300 450 600 TITLE Figure 18. CCD-MODE DNL at 18 MHz –2 –4 – ...
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... S/H Q2 Figure 24. CDS Block Diagram The AD9803 actually uses two CDS circuits in a “ping pong” fashion to allow the system more acquisition time. In this way, the output from one of the two CDS blocks will be valid for an entire clock cycle. Thus, the bandwidth requirement of the subsequent gain stage is reduced as compared to that for a single- channel CDS system ...
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... In some applications, the AD9803’s input may be exposed to large signals from the CCD, either during blanking intervals or “high speed” modes. If the signals are larger than the AD9803’ p-p input signal range, then the on-chip input circuitry may saturate. Recovery time from a saturated state could be substantial ...
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... CDS architecture of the AD9803. The digital offset correction tracks the black level of the even and odd channels, applying the necessary digital cor- rection value to keep them balanced. There is an additional two cycle delay when using the offset correction, resulting in pipe- line delay of 7 ADCCLK cycles (see Figure 1) ...
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... AD9803 SERIAL INTERFACE SPECIFICATIONS SDATA SELECT MODES PGA DAC1 DAC2 MODES2 a0–a1 b0–b1 A-REG B-REG (a) OPERATION MODES (b) OUTPUT MODES h0–h7 g0–g7 H-REG G-REG (g) DAC1 INPUT (h) DAC2 INPUT SDATA SCK SL RNW SDATA SCK ...
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... Clamp Level LSBs 48 LSBs 64 LSBs 16 LSBs CCD-Gain Minimum Maximum –15– AD9803 AUX-Gain Minimum Maximum DAC1 Output Minimum Maximum ...
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... ICs. Table I outlines the differences. The circuit of Figure 38 shows the necessary connections for the AD9803 when used in an existing AD9801 socket. The power- on reset in the AD9803 assures that the device will power-up in CCD-mode, with analog PGA gain control. Table I. AD9801/AD9803 Pin Differences Pin No ...
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... AD9803 PGACONT2 PGACONT1 (MSB) 11 DRVDD 0 0.1 F –17– AD9803 SDATA SCK SL VOUT2 VOUT1 0 ADCIN 36 AUXCONT 35 AUXIN 34 0.1 F ACVDD 33 0.1 F CLPBYP 32 ACVSS CCDBYP1 28 ...
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... Figure 38. Recommended Circuit for AD9801 Sockets V DD 0.1 F 0.1 F 1 ADCIN AUXCONT AUXIN ACVDD CLPBYP ACVSS AD9803 PGACONT2 PGACONT1 CCDBYP1 PIN DIN CCDBYP2 CLPDM SHD SHP CLPOB 0.1 F PBLK STBY ADCCLK – ...
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... MAX 0.354 (9.00) BSC 0.030 (0.75) 0.057 (1.45) 0.276 (7.0) BSC 0.030 (0.75) 0.018 (0.45) 0.053 (1.35) 0.018 (0.45 SEATING PLANE TOP VIEW (PINS DOWN) 0.076 MAX MIN 0° MIN 0° – 7° 0.007 (0.18) 0.009 (0.225) 0.019 (0.5) 0.004 (0.09) BSC 0.006 (0.17) –19– AD9803 ...