AD9888 Analog Devices, AD9888 Datasheet

Page 1

... MHz supports resolutions up to UXGA (1600 × 1200 at 75 Hz). For ease of design and to minimize cost, the AD9888 is a fully integrated interface solution for flat panel displays. The AD9888 includes an analog interface with a 205 MHz triple ADC with internal 1 ...

Page 2

... Binary IV 3.0 3.3 3.6 3.0 IV 2.2 3.3 3.6 2.2 IV 3.0 3.3 3.6 3.0 V 200 850 1050 –2– AD9888KS-170 AD9888KS-205 Typ Max Min Typ Max 8 8 ±0.6 +1.25/–1.0 ±0.8 +1.50/–1.0 +1.50/–1.0 +1.80/–1.0 ±0.75 ±2.25 ±1.0 ±3.75 ±2.75 ±4.25 Guaranteed Guaranteed 0.5 0.5 1.0 100 100 ...

Page 3

... JC Thermal Resistance —Junction-to-Ambient JA Thermal Resistance NOTES 1 AD9888KS-100 specifications are tested at 100 MHz. AD9888KS-140 specifications are tested at 140 MHz. 2 See Figure 23. 3 VCO Range = 10, Charge Pump Current = 100, PLL Divider = 1693. 4 VCO Range = 11, Charge Pump Current = 100, PLL Divider = 2159. 5 DEMUX = 1, DATACK and DATACK Load = 15 pF, Data Load = 5 pF ...

Page 4

... GND 28 GND 29 CKINV 30 CLAMP SDA 31 32 SCL GND GND PIN CONFIGURATION PIN 1 IDENTIFIER AD9888 TOP VIEW (Not to Scale) –4– 102 V DD 101 GND 100 GND 99 GND ...

Page 5

... Port B Outputs of Converter “Green.” Bit 7 is the MSB. Port A Outputs of Converter “Blue.” Bit 7 is the MSB. Port B Outputs of Converter “Blue.” Bit 7 is the MSB. Data Output Clock Data Output Clock Complement –5– AD9888 Value Pin No ...

Page 6

... CKEXT External Clock Input (Optional) This pin may be used to provide an external clock to the AD9888 in place of the clock internally generated from HSYNC enabled by programming the External Clock Register to 1 (15H, Bit 0). When an external clock is used, all other internal functions operate normally. When unused, this pin should be tied through a 10 kΩ resistor to GROUND, and the External Clock Register programmed to 0 ...

Page 7

... They are produced by the internal clock generator and are synchronous with the internal pixel sampling clock. When the AD9888 is operated in single-channel mode, the output frequency is equal to the pixel sampling frequency. When operated in dual-channel mode, the clock frequency is one-half the pixel frequency the out put data frequency. ...

Page 8

... PLL and help the user design for optimal performance. The designer should provide “quiet,” noise-free power to these pins. GND Ground The ground return for all circuitry on chip recommended that the AD9888 be assembled on a single solid ground plane, with careful attention paid to ground current paths. Serial Port (2-Wire) SDA ...

Page 9

... CLAMP pin at the appropriate time (with External Clamp = 1). The polarity of this signal is set by the Clamp Polarity (Register 0FH, Bit 6). A simpler method of clamp timing employs the AD9888 internal clamp timing generator. The Clamp Placement Register is programmed with the number of pixel times that should pass after the trailing edge of HSYNC before clamping starts ...

Page 10

... Considerable care has been taken in the design of the AD9888’s clock generation circuit to minimize jitter. As indicated in Figure 5, the clock jitter of the AD9888 is less than 9% of the total pixel time in all operating modes, making the reduction in the valid sampling time due to jitter negligible. ...

Page 11

... AD9888 K Gain VCO (MHz/V) 150 150 150 180 Current 010 100 100 100 100 101 011 011 011 100 100 101 011 011 011 100 100 100 ...

Page 12

... AD9888 4. The 5-Bit Phase Adjust Register. The phase of the generated sampling clock may be shifted to locate an optimum sampling point within a clock cycle. The Phase Adjust Register pro- vides 32 phase-shift steps of 11.25° each. The Hsync signal with an identical phase shift is available through the HSOUT pin ...

Page 13

... TIMING The following timing diagrams show the operation of the AD9888 analog interface in all clock modes. The part establishes timing by sending the sample that corresponds to the pixel digitized when the leading edge of Hsync occurs sent to the “A” data port. In dual-channel mode, the next sample is to the “B” port. Future samples are alternated between the “ ...

Page 14

... AD9888 P0 P1 RGBIN HSYNC PXCK HS 8 PIPE DELAY ADCCK DATACK DOUTA HSOUT RGBIN HSYNC PXCK HS 8 PIPE DELAY ADCCK DATACK DOUTA HSOUT Figure 14. Single-Channel Mode, Two Pixels/Clock (Even Pixels RGBIN HSYNC PXCK HS ADCCK ...

Page 15

... DOUTB HSOUT Figure 18. Dual-Channel Mode, Interleaved Outputs, Two Pixels/Clock (Even Pixels) REV VARIABLE DURATION PIPE DELAY Figure 17. Dual-Channel Mode, Parallel Outputs D0 VARIABLE DURATION –15– AD9888 VARIABLE DURATION ...

Page 16

... AD9888 RGBIN HSYNC PXCK HS ADCCK DATACK DOUTA DOUTB HSOUT Figure 19. Dual-Channel Mode, Interleaved Outputs, Two Pixels/Clock (Odd Pixels RGBIN HSYNC PXCK HS ADCCK DATACK DOUTA DOUTB HSOUT Figure 20. Dual-Channel Mode, Parallel Outputs, Two Pixels/Clock (Even Pixels) ...

Page 17

... DATACK GOUTA ROUTA HSOUT 2-WIRE SERIAL REGISTER MAP The AD9888 is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to write and read the Control Registers through the 2-line serial interface port. Read and Hex Write or Default ...

Page 18

... AD9888 Read and Hex Write or Default Address Read Only Bits Value 0EH R/W 7:0 0******* Sync Control *1****** **0***** ***0**** ****0*** *****0** ******0* *******0 0FH R/W 7:1 0******* *1****** **0***** ***0**** ****1*** *****1** ******1* 10H R/W 7:3 01111*** Sync-on-Green *****0** ******0* *******0 11H R/W 7:0 00100000 Sync Separator 12H R/W 7:0 00000000 Pre-COAST 13H R/W 7:0 00000000 Post-COAST Table V. Control Register Map (continued) ...

Page 19

... Test Register 18H RO 7:0 19H RO 7:0 *The AD9888 only updates the PLL divide ratio when the LSBs are written to (Register 02H). REV. B Table V. Control Register Map (continued) Register Name Function Sync Detect Bit 7—Hsync Detect set to Logic 1 if Hsync is present on the analog interface, else it is set to Logic 0. Bit 6— ...

Page 20

... The four least significant bits of the 12-bit PLL divide ratio PLLDIV. The operational divide ratio is PLLDIV + 1. The power-up default value of PLLDIV is 1693 (PLLDIVM = 69H, PLLDIVL = DxH). The AD9888 updates the full divide ratio only when this register is written to. CLOCK GENERATOR CONTROL 03 ...

Page 21

... The leading edge of the Hsync output is triggered by the internally generated, phase adjusted PLL feedback clock. The AD9888 then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase adjusted. ...

Page 22

... AD9888 Table XI. Active Hsync Override Settings Override Result 0 Auto determines the active interface. 1 Override, Bit 3, determines the active interface. The default for this register Active Hsync Select This bit is used under two conditions used to select the active Hsync when the override bit is set (Bit 4). ...

Page 23

... Hsync period. The default 7-0 Post-COAST This register allows the COAST signal to be applied following to the Vsync signal. This is necessary in cases where post-equalization pulses are present. The step size for this control is one Hsync period. The default is 0. –23– AD9888 ...

Page 24

... AD9888 14 7 Hsync Detect This bit is used to indicate when activity is detected on the selected Hsync input pin. If HSYNC is held high or low, activity will not be detected. Table XXV. Hsync Detection Results Detect Function 0 No Activity Detected 1 Activity Detected The sync processing block diagram shows where this function is implemented ...

Page 25

... A Logic 0 enables the internal PLL that generates the pixel clock from an externally provided HSYNC. A Logic 1 enables the external CKEXT input pin. In this mode, the PLL Divide Ratio (PLLDIV) is ignored. The clock phase adjust (PHASE) is still functional. The power-up default value is EXTCLK = 0. –25– AD9888 Output Format U/V Y High Impedance ...

Page 26

... Any base address higher than 19H will not produce an acknowledge signal. Data are read from the control registers of the AD9888 in a similar manner. Reading requires two data transfer operations. The base address must be written with the R/W bit of the slave address byte Low to set up a sequential read operation ...

Page 27

... Hsync signal. So, it rejects any signal shorter than a threshold value, which is somewhere between an Hsync pulsewidth and a Vsync pulsewidth. The sync separator on the AD9888 is an 8-bit digital counter with a 5 MHz clock. It works independently of the polarity of the composite sync signal. (Polarities are determined elsewhere on the chip ...

Page 28

... POLARITY MUX4 DETECT Figure 25. Sync Processing Block Diagram the opposite side of the PC board from the AD9888, as that interposes resistive vias in the path. The bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power plane => ...

Page 29

... Any noise that gets onto the Hsync input trace will add jitter to the system. Therefore, minimize the trace length and do not run any digital or other high frequency traces near it. Voltage Reference Bypass with a 0.1 µF capacitor. Place it as close to the AD9888 pin as possible. Make the ground connection as short as possible. –29– AD9888 ...

Page 30

... AD9888 COPLANARITY 0.10 MAX OUTLINE DIMENSIONS 128-Lead Metric Quad Flat Package [MQFP] (S-128A) Dimensions shown in millimeters 17.45 17.20 16.95 14.20 3.40 14.00 MAX 13.80 1.03 128 1 0.88 0.73 SEATING PLANE TOP VIEW (PINS DOWN 0.50 0.50 2.90 0.25 BSC 2.70 2.50 –30– 103 102 20.20 23.45 20.00 23.20 19.80 22. 0.27 0.17 REV. B ...

Page 31

... Sheet changed from REV REV. A. Change to TITLE–PART NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Change to PIN FUNCTION DETAIL, CKINV section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Change to Figure Change to Figure Change to Figure Change to Figure Change to Figure Change to Figure Change to Figure Change to Figure REV. B –31– AD9888 Page ...

Page 32

–32– ...