MPC9446 Integrated Device Technology, Inc., MPC9446 Datasheet
MPC9446
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MPC9446 Summary of contents
Page 1
... V supporting mixed voltage applications. The FSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the three output banks. The MPC9446 can be rese,t and the outputs are disabled by deasserting the MR/OE pin (logic high state). Asserting MR/OE will enable the outputs. ...
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... MPC9446 Bank A QA0 QA1 QA2 Bank B QB0 QB1 QB2 QC0 Bank C QC1 QC2 QC3 V is internally connected to V CCB 17 16 QC3 15 GND 14 QC2 13 V CCC 12 QC1 11 GND 10 QC0 9 V CCC 8 2MPC9446 REV 4 NOVEMBER 28, 2007) CC ...
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... 2 internally connected to V CCB 1 CCLK1 ÷ QA0:2 REF ÷ QB0:2 REF ÷ QC0:3 REF Internal reset outputs disabled (tristate) Max Unit Condition ±20 mA ±50 mA °C 125 3MPC9446 REV 4 NOVEMBER 28, 2007 ...
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... AC characteristics apply for parallel output termination of 50 Ω The MPC9446 is functional input and output clock frequency of 350 MHz and is characterized up to 250 MHz. 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications ...
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... AC characteristics apply for parallel output termination of 50 Ω The MPC9446 is functional input and output clock frequency of 350 MHz and is characterized up to 250 MHz. 3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications ...
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... Figure 4 show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9446 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations, a delta of only 43 ps exists between the two differently loaded outputs ...
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... MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER Pulse Generator Z = 50Ω Figure 6. CCLK0, 1 MPC9446 AC Test Reference for Figure 7. Output Transition Time Test Reference t SK(LH) The pin-to-pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device ...
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... MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE 8MPC9446 REV 4 NOVEMBER 28, 2007) ...
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... MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE 9MPC9446 REV 4 NOVEMBER 28, 2007) ...
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... MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER IDT™ / ICS™ LVCMOS CLOCK FANOUT BUFFER PACKAGE DIMENSIONS CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE PAGE 10MPC9446 REV 4 NOVEMBER 28, 2007) ...
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... MPC9446 3.3V AND 2.5V LVCMOS CLOCK FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 netcom@idt.com 408-284-8200 480-763-2056 Fax: 408-284-2775 Corporate Headquarters Asia Pacific and Japan Integrated Device Technology, Inc. Integrated Device Technology 6024 Silver Creek Valley Road Singapore (1997) Pte ...