MT90823AB Zarlink Semiconductor, MT90823AB Datasheet
MT90823AB
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MT90823AB Summary of contents
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... FE/ WFPS HCLK Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved. MT90823AP MT90823AL MT90823AB MT90823AG MT90823AB1 MT90823AP1 MT90823AL1 MT90823AG2 **Pb Free Tin/Silver/Copper Applications • Medium and large switching platforms • CTI application • ...
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... Per stream input delay control is particularly useful for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, the input stream can be individually calibrated for input frame offset using a dedicated pin. MT90823 2 Zarlink Semiconductor Inc. Data Sheet ...
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... STi10 (14mm x 20mm x 2.75mm) STi11 92 STi12 94 STi13 STi14 96 STi15 F0i 98 FE/HCLK 99 VSS CLK Figure 2 - PLCC and MQFP Pin Connections Zarlink Semiconductor Inc. MT90823 CSTo DTA 73 D15 D14 71 D13 D12 69 D11 D10 PIN PLCC ...
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... STi12 STi13 92 STi14 STi15 94 F0i FE/HCLK 96 VSS CLK VDD 98 NC 100 Figure 3 - PBGA and LQFP Pin Connections Zarlink Semiconductor Inc STo7 STo5 STo4 STo2 STo0 VSS VSS VSS STo6 STo3 STo1 ODE VSS VSS VSS ...
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... Test Mode Select (3.3 V Input with internal pull-up): JTAG signal that controls the TAP controller state transitions. TDI Test Serial Data In (3.3 V Tolerant Input with internal pull-up): JTAG serial test instructions and data are shifted in on this pin. 5 Zarlink Semiconductor Inc. Data Sheet ...
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... DS. This active low input works in conjunction with CS to enable the read and write operations. For multiplexed bus operation, this input is RD. This active low input sets the data bus lines (AD0-AD7, D8- D15) as outputs. 6 Zarlink Semiconductor Inc. Data Sheet for normal operation. This pin ...
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... CSTo Control Output (5 V Tolerant Output). This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1024 or 2048 bits per frame respectively. The level of each bit is determined by the CSTo bit in the connection memory. See External Drive Control Section. 7 Zarlink Semiconductor Inc. Data Sheet ...
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... STo0 - 7 Data Stream Output Tolerant Three-state Outputs): Serial data Output stream. These streams have selectable data rates of 2.048, 4.096 or 8.192 Mb/ connection. 8 Zarlink Semiconductor Inc. Data Sheet ...
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... The master clock frequency must always be twice the data rate. The master clock (CLK) must be either at 4.096, 8.192 or 16.384 MHz for serial data rate of 2.048, 4.096 or 8.192 Mb/s respectively. The input and output stream data rates will always be identical. MT90823 9 Zarlink Semiconductor Inc. Data Sheet ...
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... This mode requires a CLK of 16.384 MHz and allows a maximum non-blocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship between different serial data rates and the master clock frequencies. MT90823 requires a CLK of 8.192 MHz and allows a maximum non-blocking 10 Zarlink Semiconductor Inc. Data Sheet ...
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... The loopback control (LPBK) bit of each connection memory location allows the ST-BUS output data to be looped backed internally to the ST-BUS input for diagnostic purposes. MT90823 Master Clock Matrix Channel Required (MHz) Capacity 4.096 512 x 512 8.192 1,024 x 1,024 16.384 2,048 x 2,048 Table 1 - Switching Configuration 11 Zarlink Semiconductor Inc. Data Sheet ...
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... This circuit uses the level of the DS/RD input pin at the rising edge of AS/ALE to identify the appropriate bus timing connected to the MT90823. If DS/RD is high at the falling edge of AS/ALE, then the mode 1 multiplexed timing is selected. If DS/RD is low at the falling edge of AS/ALE, then the mode 2 multiplexed bus timing is selected. MT90823 12 Zarlink Semiconductor Inc. Data Sheet ...
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... Delay for Constant Throughput Delay Mode (m - output channel number input channel number ( time-slots (m- 1) time-slots 128 + (128 - n) + (m- 1) time-slots 13 Zarlink Semiconductor Inc. Data Sheet m > n+2 m-n time-slots m-n time-slots m-n time-slots ...
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... The loopback bit should be used for diagnostic purpose only; this bit should be set to zero for normal operation. If all LPBK bits are set high for all connection memory locations, the associated ST-BUS output channel data is internally looped back to the ST-BUS input channel (i.e., SToN channel m data loops back to STi N channel m). MT90823 14 Zarlink Semiconductor Inc. Data Sheet ...
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... Ch 126 127 OSB bit in IMS register Don’t Care Don’t care 15 Zarlink Semiconductor Inc. Data Sheet Location (Note 2) (Note 3) (Note 4) ST-BUS Output Driver Status Per Channel High Impedance High Impedance Enable Enable ...
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... Table 7 - Valid Address lines for Different Bit Rates MT90823 0000 . MBP Description Table 6 - Control (CR) Register Bits 16 Zarlink Semiconductor Inc. Data Sheet STA3 STA2 STA1 STA0 Valid Address Lines A4, A3, A2, A1, A0 A5, A4, A3, A2, A1, A0 A6, A5, A4 A3, A2, A1, A0 ...
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... BPD BPD BPD BPD BPD Description Data Rate Selected 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Reserved 17 Zarlink Semiconductor Inc. Data Sheet BPE OSB SFE DR1 DR0 Master Clock Required 4.096 MHz 8.192 MHz 16.384 MHz Reserved ...
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... These bits are reset to zero when the SFE bit of the IMS register changes from (FD10 = MSB, FD0 = LSB) Table 10 - Frame Alignment (FAR) Register Bits MT90823 , FD10 FD9 FD8 FD7 FD6 FD5 Description 18 Zarlink Semiconductor Inc. Data Sheet FD4 FD3 FD2 FD1 FD0 ...
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... Offset Value Input Figure 4 - Example for Frame Alignment Measurement MT90823 (FD[10: (FD11 = 0, sample at CLK low phase (FD[10: (FD11 = 1, sample at CLK high phase) 19 Zarlink Semiconductor Inc. Data Sheet ...
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... OF101 OF100 DLE10 OF92 OF91 OF90 FOR2 register OF141 OF140 DLE14 OF132 OF131 OF130 FOR3 register Description 20 Zarlink Semiconductor Inc. Data Sheet DLE1 OF02 OF01 OF00 DLE0 DLE5 OF42 OF41 OF40 DLE4 ...
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... Bit 7 Bit 7 Bit 7 denotes the 3/4 point of the bit cell Bit 0 Bit 0 Bit 0 denotes the 3/4 point of the bit cell 21 Zarlink Semiconductor Inc. Data Sheet Corresponding Offset Bits OFn2 OFn1 OFn0 DLEn ...
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... SAB0 CAB6 CAB5 Description Table 13 - Connection Memory Bits CAB Bits Used to Determine the Source Channel of the Connection CAB4 to CAB0 (32 channel/input stream) CAB5 to CAB0 (64 channel/input stream) CAB6 to CAB0 (128 channel/input stream) 22 Zarlink Semiconductor Inc. Data Sheet CAB4 CAB3 CAB2 CAB1 ...
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... TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. MT90823 23 Zarlink Semiconductor Inc. Data Sheet ...
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... The LSB bit in the device identification register is the first bit clocked out. The MT90823 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out. All tristate enable bits are active high. MT90823 LSB 24 Zarlink Semiconductor Inc. Data Sheet ...
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... AD6 47 48 AD5 50 51 AD4 53 54 AD3 56 57 AD2 59 60 AD1 62 63 AD0 AS/ALE CS R DS/RD Table 14 - Boundary Scan Register Bits 25 Zarlink Semiconductor Inc. Data Sheet Input Scan Cell ...
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... STo13 106 107 STo12 108 109 STo11 110 111 STo10 112 113 STo9 114 115 STo8 116 117 Table 14 - Boundary Scan Register Bits (continued) 26 Zarlink Semiconductor Inc. Data Sheet Input Scan Cell ...
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... Figure 6 - Switch Matrix with Serial Stream at Various Bit Rates MT90823 16 Streams MT90823 #1 16 Streams MT90823 #2 MT90823 #3 MT90823 #4 27 Zarlink Semiconductor Inc. Data Sheet OUT Bit Rate Size of (IN/OUT) Switch Matrix 2.048 Mb/s 1,024 - Channel Switch 4.096 Mb/s 2,048 - Channel Switch 8.192 Mb/s 4,096 - Channel Switch ...
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... The DACS switching matrix that formerly required 256 MT8986 devices in a square (16 x 16) configuration can now be provided by 64 MT8986 and 16 MT90823 devices (see Figure 8). MT90823 MT90823 Frame Alignment Evaluation circuit External FE CLK FP Mux input , as specified in the AC Electrical Characteristic table. 28 Zarlink Semiconductor Inc. Data Sheet STo[0:15] Central Timing Source ...
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... Streams Switch Matrix (Figure 6) Figure 9 - 8,192 x 8,192 Channel Switch Matrix MT90823 8,192 x 8,192 channel Switch Matrix Sixteen MT90823 (8 Mb/s mode) (See Figure 9) x 4,096 x 4,096 Switch Matrix (Figure 6) 4,096 x 4,096 Switch Matrix (Figure 6) 29 Zarlink Semiconductor Inc. Data Sheet 32 Streams OUT 32 Streams ...
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... Voltages are with respect to ground (V Sym. Min. Typ. Max. T -40 + 3 Zarlink Semiconductor Inc. Data Sheet STo0 256-channel out STo1 (8.192 Mb/s per channel) STi0 256-channel in STi1 (8.192 Mb/s per channel) Min. Max. Units -0 0.3 5 ...
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... 0. Sym. Level Units Zarlink Semiconductor Inc. Data Sheet Max. Units Test Conditions 15 mA Output unloaded 0. µA 15 µA 50 0≤<V≤V See DD Note - 0.4 V ...
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... HCP t 85 150 HCH t 85 150 HCL -10 10 DIF 32 Zarlink Semiconductor Inc. Data Sheet Notes ns WFPS Pin = WFPS Pin = 0 ns WFPS Pin = 0 ns WFPS Pin = WFPS Pin = WFPS Pin = 0 ns ...
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... FPH t SOD Bit 7, Channel 0 Bit 6, Channel SIS SIH Bit 7, Channel 0 Bit 6, Channel 0 or 8.192 Mb/s, when WFPS pin = 0. 33 Zarlink Semiconductor Inc. Data Sheet Test Conditions =30pF =200pF L R =1K, C =200pF, See Note =1K, C ...
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... SOD Bit 0, Ch 127 Bit Bit SIS SIH Bit 0, Ch 127 Bit Bit with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Bit 2, Channel 0 ...
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... Valid Data HiZ STo t ZD Valid Data HiZ STo t XCD CSTo Figure 14 - Serial Output and External Control ODE t t ODE ODE STo Valid Data HiZ Figure 15 - Output Driver Enable (ODE) 35 Zarlink Semiconductor Inc. Data Sheet HiZ CT ...
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... CSW t 20 DSW t 122 SWD t 5 DHW t AKD 43/43 760/750 400/390 220/210 t 22 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =150pF =150pF, R =1K Note 1. ns ...
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... HiZ ADDRESS D8-D15 t ALRD CS t CSR CSW t ALWR DTA Figure 16 - Multiplexed Bus Timing (Mode 1) MT90823 HiZ DATA SWD DSW t DDR t AKD 37 Zarlink Semiconductor Inc. Data Sheet HiZ CT t CSRW DHR DHW t AKH V CT ...
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... RWS t 5 RWH DHR t 10 DSH t AKD 43/43 760/750 400/390 220/210 t 22 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =150pF =150pF, R =1K Note 1 ...
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... RD CS DTA Figure 17 - Multiplexed Bus Timing (Mode2) MT90823 t RWS t t DSH ASW t t ADS ADH t SW HiZ ADDRESS HiZ ADDRESS t CSS t AKD 39 Zarlink Semiconductor Inc. Data Sheet RWH DHW DWS V DATA CT t DHR V DATA CT t CSH V CT ...
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... DHR t 0 DSW t 122 SWD t 5 DHW t AKD 43/43 760/750 400/390 220/210 t 22 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =150pF =150pF Note ...
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... D8-D15 WRITE DTA Figure 18 - Motorola Non-Multiplexed Bus Timing MT90823 t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t t DSW SWD VALID WRITE DATA t DDR t AKD 41 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DHR DHW V CT ...
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... Zarlink Semiconductor 2002 All rights reserved. 1 ISSUE ACN 213934 20Jan03 DATE APPRD. Package Code : GA Previous package codes: ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...