MVTX2604AG Zarlink Semiconductor, MVTX2604AG Datasheet
MVTX2604AG
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... Figure 1 - MVTX2604 System Block Diagram Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. Managed 24-Port 10/100 Port 1 Gb MVTX2604AG • Provides port based and ID tagged VLAN support (IEEE 802.1Q 255 VLANs • ...
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... Hardware auto-negotiation through serial management interface (MDIO) for Ethernet ports • Built-in reset logic triggered by system malfunction • Built-in self test for internal and external SRAM 2 • EEPROM for configuration • 553 BGA package MVTX2604 2 Zarlink Semiconductor Inc. Data Sheet ...
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... SNMP Management frames can be received and transmitted via the CPU interface creating a complete network management solution. The MVTX2604 is fabricated using 0.25 micron technology. Inputs, however, are 3.3 V tolerant, and the outputs are capable of directly interfacing to LVTTL levels. The MVTX2604 is packaged in a 553-pin Ball Grid Array package. MVTX2604 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.0 Search Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 Search Engine Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.2 Basic Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 Search, Learning, and Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.1 MAC Search 5.3.2 Learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.3 Aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.4 VLAN Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 MAC Address Filtering 5.5 Quality of Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.6 Priority Classification Rule 5.7 Port and Tag Based VLAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.7.1 Port-Based VLAN MVTX2604 Table of Contents 4 Zarlink Semiconductor Inc. Data Sheet ...
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... SCAN LINK and SCAN COL interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.0 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 LED Interface Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2 Port Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.3 LED Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13.0 Hardware Statistics Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1 Hardware Statistics Counters List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.2 IEEE 802.3 HUB Management (RFC 1516 13.2.1 Event Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.2.1.1 Readablectet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.2.1.2 ReadableFrame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.2.1.3 FCSErrors 13.2.1.4 AlignmentErrors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 MVTX2604 Table of Contents 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Group 1 Address VLAN Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.5.1 AVTCL – VLAN Type Code Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.5.2 AVTCH – VLAN Type Code Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.5.3 PVMAP00_0 – Port 00 Configuration Register 14.5.4 PVMAP00_1 – Port 00 Configuration Register 14.5.5 PVMAP00_2 – Port 00 Configuration Register MVTX2604 Table of Contents 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Group 3 Address CPU Port Configuration Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 14.8.1 MAC0 – CPU Mac address byte 14.8.2 MAC1 – CPU Mac address byte 14.8.3 MAC2 – CPU Mac address byte 14.8.4 MAC3 – CPU Mac address byte MVTX2604 Table of Contents 7 Zarlink Semiconductor Inc. Data Sheet ...
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... C4RS – Class 4 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14.10.21 C5RS – Class 5 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14.10.22 C6RS – Class 6 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 14.10.23 C7RS – Class 7 Reserve Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 14.10.24 QOSCn - Classes Byte Limit Set 14.10.25 Classes Byte Limit Set 14.10.26 Classes Byte Limit Set MVTX2604 Table of Contents 8 Zarlink Semiconductor Inc. Data Sheet ...
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... MIRROR1_DEST – Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.12.3 MIRROR2_SRC – Port Mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.12.4 MIRROR2_DEST – Port Mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.13 Group F Address CPU Access Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 14.13.1 GCR-Global Control Register 115 14.13.2 DCR-Device Status and Signature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 MVTX2604 Table of Contents 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Gigabit Media Independent Interface - Port 166 15.8.5 Ten Bit Interface - Port 167 15.8.6 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.8.7 SCANLINK SCANCOL Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.9 MDIO Input Setup and Hold Timing 171 15.9.1 I2C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.9.2 Serial Interface Setup Timing 173 MVTX2604 Table of Contents 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 36 - MDIO Input Setup and Hold Timing 171 Figure 37 - MDIO Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Figure 38 - I2C Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Figure 39 - I2C Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Figure 40 - Serial Interface Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Figure 41 - Serial Interface Output Delay Timing 173 MVTX2604 List of Figures 11 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 22 - Output Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 23 - Input Setup Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table Characteristics – LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 25 - SCANLINK, SCANCOL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 26 - MDIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 27 - I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 28 - Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 MVTX2604 List of Tables 12 Zarlink Semiconductor Inc. Data Sheet ...
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... Transmit processes. The PCS Auto negotiation process allows the MVTX2604 to exchange configuration information between two devices that share a link segment and to automatically configure the link for the appropriate speed of operation for both devices. MVTX2604 15 Zarlink Semiconductor Inc. Data Sheet ...
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... MAC address Control Table (MCT) Link Table - The MCT Link Table stores the linked list of MCT entries that have collisions in the external MAC Table. Note that the external MAC table is located in the external SRAM Memory. MVTX2604 16 Zarlink Semiconductor Inc. Data Sheet 2 C interface, which ...
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... FRAME DATA REG CONFIG DATA REG (Addr = 010) 8 bit internal data bus CPU INTERNAL FRAME RECEIVE FIFO 17 Zarlink Semiconductor Inc. Data Sheet 2 C interface at bootup, or via a CONTROL (Addr = 011) BLOCK REG 8/16 bit internal data bus 8/16 bit internal data bus CPU CONTROL ...
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... Note: Memory read and write requests by the CPU may include VLAN table, spanning tree, statistic counters and similar updates. In addition, there are nine types of Control frames generated by the MVTX2604 and sent to the CPU: • Interrupt CPU when statistics counter rolls over MVTX2604 18 Zarlink Semiconductor Inc. Data Sheet ...
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... SDA line during the acknowledge pulse so that it remains stable Low during the High period of this clock pulse. An acknowledgment pulse follows every byte transfer. MVTX2604 ACK DATA 1 (8 bits) ACK DATA Zarlink Semiconductor Inc. Data Sheet 2 C interface at ACK DATA M ACK STOP C Interface ...
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... Any command can be aborted in the middle by sending a ABORT pulse to the MVTX2600AG. A START command is detected when D0 is sampled high when STROBE- rise and D0 is sampled low when STROBE- fall. An ABORT command is detected when D0 is sampled low when STROBE- rise and D0 is sampled high when STROBE- fall. MVTX2604 20 Zarlink Semiconductor Inc. Data Sheet ...
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... MVTX2604 A9 A10 A11 A11 W A9 A10 COMMAND DATA R A9 A10 A11 ... A10 A11 A9 COMMAND DATA Zarlink Semiconductor Inc. Data Sheet 2 extra clock cycles after 2 Extra clocks after last last transfer transfer ...
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... When the port control module determines that there is room in the MAC Transmission FIFO (TxFIFO) for another frame, it requests the handle of a new frame from the TxQ manager. The TxQ manager chooses among the head-of-line (HOL) frames from the per-class queues for that port using a Zarlink Semiconductor scheduling algorithm. ...
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... Frame forwarding to the CPU port is nearly the same as forwarding to a regular transmission port. The only difference is in frame scheduling. Instead of using the patent-pending Zarlink Semiconductor scheduling algorithms, scheduling for the CPU port is simply based on strict priority. That is, a frame in a high priority queue will always be transmitted before a frame in a lower priority queue ...
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... When the CPU writes an entry to the VLAN Index Mapping Table it has to write the same data in bank A and bank B. Search engine data is written to both banks in parallel. In this way, a search engine read operation can be performed by either bank at any time without a problem. MVTX2604 SRAM TX DMA RX DMA RX DMA 16-23 0-7 24 Zarlink Semiconductor Inc. Data Sheet RX DMA 8-15 16-23 ...
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... The maximum system memory requirement is 4 MB. If less memory is desired, the configuration can scale down. Memory Configuration Bank A Bank Memory Map MVTX2604 Tag based VLAN Frame Buffer Disable 1 K Enable 1 K Disable 2 K Enable Zarlink Semiconductor Inc. Data Sheet Max MAC Address 63.5 K ...
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... In tag based VLAN mode, if the frame is unicast, and the destination port is not a member of the correct VLAN, then the frame is dropped; otherwise, the frame is forwarded. If the frame is multicast, this same table is used to indicate MVTX2604 26 Zarlink Semiconductor Inc. Data Sheet ...
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... VLAN Index port association table (internal memory). MVTX2604 VIX4 VIX3 VIX2 … … … … … … VIX4092 VIX4091 VIX4090 Table 1 - VLAN Index Mapping Table 27 Zarlink Semiconductor Inc. Data Sheet VIX1 VIX0 … … … … VIX4089 VIX4088 ...
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... In a congested network or when a low-performance switch/router is overloaded, “best effort” becomes unsuitable for delay-sensitive traffic and mission-critical data transmission. MVTX2604 CPU P23 P22 …… Zarlink Semiconductor Inc. Data Sheet ...
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... Fix Port Priority ? No Yes TOS Precedence over VLAN? (FCR Register, Bit VLAN Tag ? Yes Use Logical Port Use VLAN Priority Use Logical Port Figure 5 - Priority Classification Rule 29 Zarlink Semiconductor Inc. Data Sheet Use Default Port Settings IP Frame ? Yes No Use TOS Yes ...
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... VLAN Port” message is sent to the CPU. A filter can be applied to discard the packet if the source port is not a member of the VLAN. MVTX2604 Destination Port Numbers Bit Map 26 … Table 3 - PVMAP Register 30 Zarlink Semiconductor Inc. Data Sheet ...
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... Layer 1 chipselect pin Bank A and Bank B Bank A and Bank B 1 M/bank 2 M/bank 1 M/bank (SBRAM) (SBRAM) (ZBT SRAM Zarlink Semiconductor Inc. Data Sheet Connections Connect 0E# and WE# Connect 0E0# and WE0# Connect 0E1# and WE1# 2 M/bank (ZBT SRAM ...
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... Bank Two Layers) Data LB_D[63:32] Data LB_D[31:0] SRAM Memory Memory 128 K 32 bits SRAM Memory Memory 128 K 32 bits Address LB_A[19:3] 32 Zarlink Semiconductor Inc. Data Sheet Memory 128 K 32 bits SRAM SRAM Memory 128 K 128 K 32 bits 32 bits SRAM SRAM Memory ...
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... Data LB_D[63:32] Data LB_D[31:0] ZBT Memory Memory 128 K 32 bits 32 bits ZBT Memory Memory 128 K 32 bits 32 bits Address LB_A[19:3] 33 Zarlink Semiconductor Inc. Data Sheet Memory 256 K 32 bits ZBT ZBT Memory 128 K 128 K 32 bits ZBT ZBT Memory 128 K 128 K ...
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... The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of the destination port. MVTX2604 Bank One Layer) Data LB_D[63:32] Data LB_D[31:0] ZBT ZBT Memory Memory 256 K 256 K 32 bits 32 bits Address LB_A[20:3] 34 Zarlink Semiconductor Inc. Data Sheet ZBT Memory 256 K 32 bits ...
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... Furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing and their relative importance. The manager can then subdivide the applications into classes and set up a service contract with each. The contract may consist MVTX2604 35 Zarlink Semiconductor Inc. Data Sheet ...
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... Apps: emails, file backups. Latency: < desired, but not critical. Drop: No drop if P1 not oversubscribed. Table 7 - Two-dimensional World Traffic 36 Zarlink Semiconductor Inc. Data Sheet High Drop Probability (high-drop) Apps: training video. Latency: < 1 ms. Drop: No drop if P3 not oversubscribed; first P3 to drop otherwise ...
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... Gbps port, P7 and P6 are both SP classes and P7 has strict priority over P6. In this case, the delay bounds per class are 0.32 ms for P5, 0.64 ms for P4, 1.28 ms for P3, and 2.56 ms for P2. MVTX2604 P2 P1 Delay Bound WFQ Delay Bound WFQ 37 Zarlink Semiconductor Inc. Data Sheet ...
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... P0 and P1 for a Gigabit port) are treated as best effort from a dropping perspective, though they still are assured a percentage of bandwidth from a WFQ scheduling perspective. What this means is that these particular queues are only affected by dropping when the global buffer count becomes low. MVTX2604 38 Zarlink Semiconductor Inc. Data Sheet ...
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... Mbps when measured over an interval of 10 ms, we can also adjust the maximum number of bytes that can be transmitted at full line rate in any single burst. Suppose we wish this limit MVTX2604 31:16 15:0 Maximum burst size Number of bytes 39 Zarlink Semiconductor Inc. Data Sheet ...
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... When the priority section is full or the packet has priority the frame is allocated in the shared poll. Once the shared poll is full the frames are allocated in the section reserved for the source port. MVTX2604 JBKB P1 JCKB Table 10 - WRED Drop Thresholds 40 Zarlink Semiconductor Inc. Data Sheet High Drop Low Drop 100% ...
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... In addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. The function of buffer management is to make sure that such dropping causes as little blocking as possible. MVTX2604 per-source reservations 41 Zarlink Semiconductor Inc. Data Sheet shared pool S per-source reservations (2 G) ...
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... Xoff was triggered. All ports are continuously monitored for congestion and a port is identified as uncongested when its queue occupancy falls below a fixed threshold. When all those ports that were originally marked as congested in the port map have become uncongested, then Xon is triggered and the 26-bit vector is reset to zero. MVTX2604 42 Zarlink Semiconductor Inc. Data Sheet ...
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... Two BE classes for 1 Gbps ports Service only when other queues are idle means that QoS not adversely affected Random early discard, with programmable levels Traffic from flow control enabled ports automatically classified Zarlink Semiconductor Inc. Data Sheet AF3 BE0 ...
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... This is because, when we select the primary forwarding port for each group we do not take the source port into account. To prevent this, we simply apply one additional filter block that forwarding port for this multicast packet. MVTX2604 44 Zarlink Semiconductor Inc. Data Sheet ...
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... An illegal port number is used to disable mirroring (which is the default setting). Bit [5] is used to select between ingress (Rx) or egress (Tx) data. MIRROR2_DEST: Sets the destination port for the second port mirroring pair. Bits [4:0] select the destination port to be mirrored. The default is port 0. MVTX2604 Port 2 Port 3 Port 6 Port 7 Port 26 (Giga 1) 45 Zarlink Semiconductor Inc. Data Sheet ...
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... RX clock respectively. The link status and collision from the PHY are multiplexed and shifted into the switch device through external glue logic. The duplex of the port can be controlled by programming the ECR register. The GPSI interface can be operated in port based VLAN mode only. MVTX2604 T[9:0] REFCLK SERDES R[9:0] RBC0 RBC1 Figure 12 - TBI Connection 46 Zarlink Semiconductor Inc. Data Sheet ...
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... MVTX2604 crs CRS_DV rxd RXD[0] rx_clk RXD[1] tx_clk TXD[1] txd TXD[0] txen TXEN 260X Figure 13 - GPSI (7WS) Mode Connection Diagram 47 Zarlink Semiconductor Inc. Data Sheet link0 Port 0 Ethernet Ethernet col0 PHY link1 col1 link2 col2 link23 col23 Port 23 Ethernet Ethernet PHY ...
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... Bit 3: Activity (where activity includes either transmission or reception of data) Bit 4: Link up Bit 5: Speed (1= 100 Mb/ Mb/s) Bit 6: Full-duplex Bit 7: Collision MVTX2604 25 cycles for link/ 24 cycles for col Drived by CPLD Drived by CPLD Total 32 cycles period Total 32 cycles period 48 Zarlink Semiconductor Inc. Data Sheet ...
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... G1 port (1= port 25 is operating at Gigabit speed; 0= speed is either 10 or 100 Mb/s depending on speed bit of Port 25) 26[2]: initialization done 26[3]: initialization start 26[4]: checksum ok 26[5]: link_init_complete 26[6]: bist_fail 26[7]: ram_error 27[0]: bist_in_process 27[1]: bist_done 12.3 LED Interface Timing Diagram The signal from the MVTX2604 to the LED decoder is shown in Figure 15. Figure 15 - Timing Diagram of LED Interface MVTX2604 49 Zarlink Semiconductor Inc. Data Sheet ...
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... Frames with Length Between 65-127 Bytes B[14] 9-L Oversize Frames B[15] 9-U Frames with Length Between 128-255 Bytes B[16] A-l B[17] A-u Frames with Length Between 256-511 Bytes B[18] B-l Frames with Length Between 512-1023 Bytes Frames with Length Between 1024-1528 Bytes B[19] B-u Fragments B[20] C-l Alignment Error B[21] C-U1 Undersize Frames B[22] C-U CRC B[23] D-l MVTX2604 50 Zarlink Semiconductor Inc. Data Sheet 0 ...
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... IEEE 802.3 HUB Management (RFC 1516) 13.2.1 Event Counters 13.2.1.1 Readablectet Counts number of bytes (i.e. octets) contained in good valid frames received. Frame size: No FCS (i.e. checksum) error No collisions MVTX2604 > 64 bytes, < 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged 51 Zarlink Semiconductor Inc. Data Sheet ...
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... VLAN Tagged > 64 bytes, < 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged > 64 bytes, > 1522 bytes if VLAN Tagged; 1518 bytes if not VLAN Tagged don’t care don’t care < 10 bytes don’t care 52 Zarlink Semiconductor Inc. Data Sheet ...
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... Sum of the following errors: FCS errors Alignment errors Frame too long Short events Late events Very long events MVTX2604 don’t care > 10 bytes, < 64 bytes don’t care don’t care any size any size > Jabber 53 Zarlink Semiconductor Inc. Data Sheet ...
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... BroadcastPkts Counts the number of good frames received and forwarded with broadcast address. Does not include non-broadcast multicast frames. 13.4.1.4 MulticastPkts Counts the number of good frames received and forwarded with multicast address. Does not include broadcast frames. MVTX2604 54 Zarlink Semiconductor Inc. Data Sheet ...
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... VLAN tag (1518 if no VLAN) < 64 bytes, 1522 bytes if VLAN tag (1518 bytes if no VLAN) don’t care don’t care < 64 bytes don’t care > 1522 bytes if VLAN tag (1518 bytes if no VLAN) don’t care 55 Zarlink Semiconductor Inc. Data Sheet ...
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... A broadcast or multicast frame qualifies as non-unicast. Furthermore, we have a counter called “frame send fail.” This keeps track of FIFO under-runs, late collisions and collisions that have occurred 16 times. MVTX2604 any size 56 Zarlink Semiconductor Inc. Data Sheet ...
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... R/W 170 R/W 171-178 R/W 200 R/W 201 R/W 202 R/W 203 R/W 204 R/W 205 R/W 206 R/W 207 R/W 208 R/W 209 R/W 57 Zarlink Semiconductor Inc. Data Sheet 2 Default Notes I C Addr (Hex) 000-01A 020 01B-035 000 NA 000 036 000 037 081 038-052 0FF 053-06D 0FF 06E-088 0FF 089-0A3 007 0A4 ...
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... R/W 20D R/W 20E R/W 20F R/W 210 R/W 211 R/W 212 R/W 220 R/W 221 R/W 222 R/W 223 R/W 224 R/W 225 R/W 226 R/W 227 R/W 228 R/W 229 R/W 58 Zarlink Semiconductor Inc. Data Sheet 2 Default Notes I C Addr (Hex) NA 000 0A6 003 NA 004 NA 005 NA 006 NA 007 NA 003 NA 019 NA 01A NA 0FF NA 0FF NA 0FF NA 0FF NA ...
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... R/W 301 R/W 302 R/W 303 R/W 304 R/W 305 R/W 306 R/W 310+N (310 - R/W 313) 323 R/W 324 RO 325 R/W 400 R/W 401 R/W 402 R/W 403 R/W 404 R/W 59 Zarlink Semiconductor Inc. Data Sheet 2 Default Notes I C Addr (Hex) NA 0FF NA 0FF NA 0FF NA 0FF NA 0FF NA 0FF NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 NA 000 ...
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... R/W 50E R/W 50F R/W 510 R/W 511 R/W 512 R/W 513 R/W 514 R/W 515 R/W 516 R/W 517- 51C R/W 51D- 522 R/W 60 Zarlink Semiconductor Inc. Data Sheet 2 Default Notes I C Addr (Hex) 0AA 0FF 0AB 000 0AC 008 0AD 000 0AE 000 0AF 000 0B0 000 0B1 000 0B2 ...
Page 59
... R/W 593 R/W 594 R/W 595 R/W 596 R/W 597 R/W 598 R/W 599 R/W 59A R/W 59B R/W 59C R/W 59D R/W 59E R/W 61 Zarlink Semiconductor Inc. Data Sheet 2 Default Notes I C Addr (Hex) 0C7-0D2 000 NA 000 0FB 08F 0FC 088 0D6-0DD 000 0DE-0E5 000 0E6 000 0E7 000 0E8 000 0E9 ...
Page 60
... R/W 607 RO 608 RO 609 R/W 60A R/W 60B R/W 700 R/W 701 R/W 702 R/W 703 R/W F00 R/W F01 RO F02 RO F03 R/W F04 RO FFF RO 62 Zarlink Semiconductor Inc. Data Sheet 2 Default Notes I C Addr (Hex) NA 000 0F0 000 0F1 000 0F2 010 N/A 000 N/A 000 N/A 000 N/A 000 N/A N/A N/A N/A 0F3 000 N/A 000 0FF ...
Page 61
... Set this bit to indicate CPU received a whole frame (transmit FIFO frame receive done), and flushed the rest of frame fragment. This bit will be self- cleared. Bit [4]: • Set this bit to indicate that the following Write to the Receive FIFO is the last one (EOF). This bit will be self-cleared. MVTX2604 63 Zarlink Semiconductor Inc. Data Sheet ...
Page 62
... CPU has to wait until this bit read a new control command Bit [3]: • Transmit FIFO has data for CPU to read (TXFIFO_RDY) Bit [4]: • Receive FIFO has space for incoming CPU frame (RXFIFO_SPOK) Bit [5]: • Transmit FIFO End Of Frame (TXFIFO_EOF) Bit [6]: • Reserve Bit [7]: • Reserve MVTX2604 64 Zarlink Semiconductor Inc. Data Sheet ...
Page 63
... When CPU reads this register, data is read from the Control Command Frame Transmit Buffer1 14.3 Indirectly Accessed registers 14.4 Group 0 Address MAC Ports Group 14.4.1 ECR1Pn: Port N Control Register Address 000 - 01A; CPU Address:0000+2xN (N = port number) Accessed by CPU, serial interface and State A-FC MVTX2604 2 C (R/ Port Mode 65 Zarlink Semiconductor Inc. Data Sheet ...
Page 64
... But MAC receiver interprets and processes flow control frames. Bit [7:6] • Spanning tree state (802.1D spanning tree protocol) Default is 11. 00 – Blocking: Frame is dropped 01 - Listening: Frame is dropped 10 - Learning: Frame is dropped. Source MAC address is learned Forwarding: Frame is forwarded. Source MAC address is learned. Zarlink Semiconductor Inc. 66 Data Sheet ...
Page 65
... WFQ credit set 1 • 10: select class byte limit set 2 and classes WFQ credit set 2 • 11: select class byte limit set 3 and classes WFQ credit set 3 MVTX2604 Reserve DisL Ftf 67 Zarlink Semiconductor Inc. Data Sheet 0 Futf ...
Page 66
... Gigabit port data path. • 0: Direct flow control disabled (default) • 1: Direct flow control enabled MVTX2604 RstA DF DI MiiA RstA 68 Zarlink Semiconductor Inc. Data Sheet ...
Page 67
... This register indicates the legal egress ports. A “1” on bit 7 means that the packet can be sent to port 7. A “0” on bit 7 means that any packet destined to port 7 will be discarded. This register works with registers 1, 2 and 3 to form a 27 bit mask to all egress ports. MVTX2604 2 C (R/ (R/ (R/W) 69 Zarlink Semiconductor Inc. Data Sheet ...
Page 68
... VLAN Mask for ports (Default FF) In Tag based VLAN Mode This registered is unused 14.5.6 PVMAP00_3 – Port 00 Configuration Register Address h89, CPU Address:h105 Accessed by CPU, serial interface and I MVTX2604 2 C (R/ Ultrust PVID 2 C (R/ (R/W) 70 Zarlink Semiconductor Inc. Data Sheet ...
Page 69
... Disable Ingress Filter. Packets with VLAN not belonging to source port are forwarded, if destination port belongs to the VLAN. Symmetric VLAN. • 1 Enable Ingress Filter. Packets with VLAN not belonging to source port are filtered. Asymmetric VLAN. • 0 Disable (Default) • 1 Force untagged output 71 Zarlink Semiconductor Inc. Data Sheet ...
Page 70
... Discard Priority Level 1 (Highest) • 0 Disable fix priority. All frames are analyzed. Transmit Priority and Discard Priority are based on VLAN Tag, TOS or Logical Port. • 1 Transmit Priority and Discard Priority are based on values programmed in bit [6:3] 72 Zarlink Semiconductor Inc. Data Sheet ...
Page 71
... CPU MAC address. • 1: One block of 32 MAC addresses are assigned to CPU. The block is defined in an increase way from the MAC address programmed in registers MAC0 to MAC5. MVTX2604 STP SM0 rPCS Zarlink Semiconductor Inc. Data Sheet 0 Vmod ...
Page 72
... VLAN Index 8’hCD has router group and the router group is VLAN Index 8’h4D Bit [6]: • VLAN Index 8’hCE has router group and the router group is VLAN Index 8’h4E Bit [7]: • VLAN Index 8’hCF has router group and the router group is VLAN Index 8’h4F MVTX2604 74 Zarlink Semiconductor Inc. Data Sheet ...
Page 73
... VLAN Index 8’hE5 has router group and the router group is VLAN Index 8’h65 Bit [6]: • VLAN Index 8’hE6 has router group and the router group is VLAN Index 8’h66 Bit [7]: • VLAN Index 8’hE7 has router group and the router group is VLAN Index 8’h67 MVTX2604 75 Zarlink Semiconductor Inc. Data Sheet ...
Page 74
... VLAN Index 8’hFA has router group and the router group is VLAN Index 8’h7A Bit [3]: • VLAN Index 8’hFB has router group and the router group is VLAN Index 8’h7B Bit [4]: • VLAN Index 8’hFC has router group and the router group is VLAN Index 8’h7C MVTX2604 76 Zarlink Semiconductor Inc. Data Sheet ...
Page 75
... ports can be selected for trunk group MVTX2604 TRUNK0_H TRUNK0_M Zarlink Semiconductor Inc. Data Sheet TRUNK0_L ...
Page 76
... Hash result 1 destination port number (Default 01) 14.7.7 TRUNK0_HASH2 – Trunk group 0 hash result 2 destination port number CPU Address:h206 Accessed by CPU, serial interface (R/W) Bit [4:0] Hash result 2 destination port number (Default 02) MVTX2604 2 C (R/ Hash Port Select Select 78 Zarlink Semiconductor Inc. Data Sheet ...
Page 77
... Port selection in unmanaged mode. Input pin TRUNK1 enable/disable trunk group 1 in unmanaged mode. • 00 Reserved • 01 Port 4 and 5 are used for trunk1 • 10 Reserved • 11 Port 4,5,6 and 7 are used for trunk1 MVTX2604 2 C (R/ Port Select 79 Zarlink Semiconductor Inc. Data Sheet ...
Page 78
... Trunk Mode. Enable Trunk group for Gigabit port 1 and 2 in managed mode. In unmanaged mode Trunk 2 is enable/disable using input pin TRUNK2. • 010 Single Ring with G1 • 100 Single Ring with G2 • 111 Dual Ring Mode MVTX2604 Zarlink Semiconductor Inc. Data Sheet ...
Page 79
... Accessed by CPU, serial interface (R/W) Bit [7:0] (Default FF) MVTX2604 HASH0_2 HASH0_1 HASH1_2 HASH1_1 HASH2_2 HASH2_1 HASH3_2 HASH3_1 Zarlink Semiconductor Inc. Data Sheet HASH0_0 HASH1_0 HASH2_0 HASH3_0 ...
Page 80
... Multicast_HASH1-2 – Multicast hash result 1 mask byte 2 CPU Address:h226 Accessed by CPU, serial interface (R/W) Bit [7:0] (Default FF) 14.7.20.7 Multicast_HASH1-3 – Multicast hash result 1 mask byte 3 CPU Address:h227 Accessed by CPU, serial interface (R/W) Bit [7:0] (Default FF) MVTX2604 0 ULTICAST HASH RESULT MASK BYTE 1 ULTICAST HASH RESULT MASK BYTE 82 Zarlink Semiconductor Inc. Data Sheet 3 1 ...
Page 81
... Accessed by CPU, serial interface (R/W) Bit [7:0] (Default FF) MVTX2604 2 ULTICAST HASH RESULT MASK BYTE 2 ULTICAST HASH RESULT MASK BYTE 2 ULTICAST HASH RESULT MASK BYTE 3 ULTICAST HASH RESULT MASK BYTE 3 ULTICAST HASH RESULT MASK BYTE 3 ULTICAST HASH RESULT MASK BYTE 83 Zarlink Semiconductor Inc. Data Sheet ...
Page 82
... MAC3 – CPU Mac address byte 3 CPU Address:h303 Accessed by CPU Bit [7:0] Byte 3 of the CPU MAC address. (Default 00) 14.8.5 MAC4 – CPU Mac address byte 4 CPU Address:h304 Accessed by CPU Bit [7:0] Byte 4 of the CPU MAC address. (Default 00) MVTX2604 MAC3 MAC2 MAC1 MAC0 84 Zarlink Semiconductor Inc. Data Sheet 0 ...
Page 83
... Bit [1]: Port 0 link change mask Bit [4]: Port 1 statistic counter wrap around interrupt mask. Refer to hardware statistic counter for interupt sources. Bit [5]: Port 1 link change mask MVTX2604 Refer to hardware statistic counter for interrupt 85 Zarlink Semiconductor Inc. Data Sheet ...
Page 84
... INTP_MASK7 – Interrupt Mask for MAC Port 14,15 CPU Address:h317 Accessed by CPU, serial interface (R/W) 14.8.16 INTP_MASK8 – Interrupt Mask for MAC Port 16,17 CPU Address:h318 Accessed by CPU, serial interface (R/W) 14.8.17 NTP_MASK9 – Interrupt Mask for MAC Port 18,19 CPU Address:h319 Accessed by CPU, serial interface (R/W) MVTX2604 86 Zarlink Semiconductor Inc. Data Sheet ...
Page 85
... WRED thresholds. Queue 0 is not subject to early drop. Packets in queue 0 are dropped only when the queue is too old. An entry is too old when it is older than the time programmed in the register TX_AGE [5:0]. CPU can dynamically program this register reading register RQSS [7:4]. MVTX2604 FQ0 SQ3 SQ2 SQ1 SQ0 87 Zarlink Semiconductor Inc. Data Sheet ...
Page 86
... Accessed by CPU, serial interface and I Bit [7:0]: High byte of the MAC address aging timer. The default setting provide 300 seconds aging time. Aging time is based on the following equation: MVTX2604 4 3 LQ0 NeQ3 NeQ2 NeQ1 0 Tx Queue Agent 2 C (R/ (R/W) 88 Zarlink Semiconductor Inc. Data Sheet 0 NeQ0 ...
Page 87
... Disable report aging VLAN port association (Default 0) 0 – Enable Report aging VLAN. VLAN is not removed by hardware. The CPU needs to remove the VLAN –port association. Bit [5 Report ARP packet to CPU (Default 0) MVTX2604 DRA DA DRD DRN 89 Zarlink Semiconductor Inc. Data Sheet 0 FL ...
Page 88
... FCB Aging time. Unit of 1ms. (Default FF) • This is for buffer aging control used to configure the buffer aging time. This function can be enabled/disabled through bootstrap pin not suggested to use this function for normal operation. MVTX2604 0 0 FCBAT 90 Zarlink Semiconductor Inc. Data Sheet ...
Page 89
... This is used to limit the amount of flooding traffic. The value in U2MR specifies how many packets are allowed to flood within the time specified by bit [6:4]. To disable this function, program U2MR to 0. (Default = 8) MVTX2604 2 C (R/ VF1c (R/ U2MR 91 Zarlink Semiconductor Inc. Data Sheet ...
Page 90
... When the packet goes out it carries the original priority. Bit [2:0]: Priority when the VLAN tag priority field is 0 (Default 0) Bit [5:3]: Priority when the VLAN tag priority field is 1 (Default 0) Bit [7:6]: Priority when the VLAN tag priority field is 2 (Default 0) MVTX2604 2 C (R/ VP1 VP0 92 Zarlink Semiconductor Inc. Data Sheet ...
Page 91
... Priority when the TOS field is 0 (Default 0) Bit [5:3]: Priority when the TOS field is 1 (Default 0) Bit [7:6]: Priority when the TOS field is 2 (Default 0) MVTX2604 2 C (R/ VP3 VP2 2 C (R/ VP6 VP5 2 C (R/ TP1 TP0 93 Zarlink Semiconductor Inc. Data Sheet ...
Page 92
... Frame drop priority when VLAN Tag priority field is 2 (Default 0) Bit [3]: Frame drop priority when VLAN Tag priority field is 3 (Default 0) MVTX2604 2 C (R/ TP3 TP2 2 C (R/ TP6 TP5 2 C (R/ FDV4 FDV3 FDV2 FDV1 94 Zarlink Semiconductor Inc. Data Sheet 1 0 FDV0 ...
Page 93
... Time base is based on register FCR [6:4] Bit [3:0] : Multicast Rate Control. Number of multicast packets allowed within the time defined in bits the Flooding Control Register (FCR). (Default 0). MVTX2604 2 C (R/ FDT4 FDT3 FDT2 FDT1 2 C (R/ Multicast Rate 95 Zarlink Semiconductor Inc. Data Sheet 0 FDT0 ...
Page 94
... Define the space in the FDB reserved for each 10/100 port and CPU. Expressed in multiples of 4 packets. For each packet 1536 bytes are reserved in the memory. MVTX2604 2 C (R/ (R/ Multicast congest threshold 2 C (R/ Buffer reservation 96 Zarlink Semiconductor Inc. Data Sheet ...
Page 95
... Shared pool buffer size Bits [7:0]: Expressed in multiples of 4 packets. Buffer reservation for shared pool. • Default: - h64 for 24+2 configuration with memory of 2 MB/bank; - h14 for 24+2 configuration with memory of 1 MB/bank; MVTX2604 2 C (R/ buffer reservation 2 C (R/ Zarlink Semiconductor Inc. Data Sheet ...
Page 96
... C6RS – Class 6 Reserve Size Address h0BF; CPU Address 515 Accessed by CPU, serial interface and I 7 Class 6 FCB Reservation Buffer reservation for class 6 (second highest priority). Granularity 1. (Default 0) MVTX2604 2 C (R/ (R/ (R/ (R/ (R/ Zarlink Semiconductor Inc. Data Sheet ...
Page 97
... A - QOSC08 – BYTE_C23 (CPU Address 51f) QOSC06 through QOSC08 represents one set of values A-C for a 10/100 port when using the Weighted Random Early Drop (WRED) scheme. MVTX2604 2 C (R/ (R/W Address h0C1, CPU Address 517 Address h0C2, CPU Address 518 (R/W): 99 Zarlink Semiconductor Inc. Data Sheet ...
Page 98
... A - QOSC23 – BYTE_C7_G2 (I C Address h0D2, CPU Address 52e) QOSC12 through QOSC17 represent the values A-F for Gigabit port 2. They are per-queue byte thresholds for random early drop. QOSC17 represents A, and QOSC12 represents F. MVTX2604 2 C (R/W (R/W) 100 Zarlink Semiconductor Inc. Data Sheet ...
Page 99
... QOSC29[6]: Flow control pause best effort traffic only 14.10.32 Classes WFQ Credit Set 2 Accessed by CPU and serial interface W0 - QOSC32[5:0] – CREDIT_C20 (CPU Address 537 QOSC33[5:0] – CREDIT_C21 (CPU Address 538 QOSC34[5:0] – CREDIT_C22 (CPU Address 539 QOSC35[5:0] – CREDIT_C23 (CPU Address 53a) MVTX2604 101 Zarlink Semiconductor Inc. Data Sheet ...
Page 100
... QOSC40 through QOSC47 represents the set of WFQ parameters for Gigabit port 24. The granularity of the numbers is 1 and their sum must be 64. QOSC47 corresponds to W7 and QOSC40 corresponds to W0. In the 2G trunk configuration, the sum of all values QOSC40 through QOSC47 must be equal to 128. MVTX2604 102 Zarlink Semiconductor Inc. Data Sheet ...
Page 101
... Shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). Shaper is limited to gigabit ports and queue P6 when strict priority. QOSC49 programs the peak rate for gigabit port 2. See Programming QoS Register application note for more information. MVTX2604 103 Zarlink Semiconductor Inc. Data Sheet ...
Page 102
... Their respective priority can be programmed via Well_Known_Port [7:0] priority register. Well_Known_Port_ Enable can individually turn on/off each Well Known Port if desired. MVTX2604 c C (R/ Rate 2 C (R/ Rate 104 Zarlink Semiconductor Inc. Data Sheet ...
Page 103
... The chip allows the CPU to define the priority Bits [3:0]: Priority setting, transmission + dropping, for logic port 0 Bits [7:4]: Priority setting, transmission + dropping, for logic port 1 (Default 00) MVTX2604 SER EFINE OGICAL ORT 2 C (R/ (R/ Priority 0 Drop 105 Zarlink Semiconductor Inc. Data Sheet (0~7) ...
Page 104
... Priority 0 - Well known port 23 for telnet applications. MVTX2604 2 C (R/ Priority 2 Drop 2 C (R/ Priority 4 Drop D L SER EFINE OGIC 2 C (R/ Priority 6 Drop 2 C (R/ (R/ Priority 0 Drop 106 Zarlink Semiconductor Inc. Data Sheet ORT AND RIORITY ...
Page 105
... Priority 6 - well know port 22 for ssh. Priority 7 – well Known port 554 for rtsp. (Default 00) MVTX2604 2 C (R/ Priority 2 Drop 2 C (R/ Priority 4 Drop K ELL NOWN 2 C (R/ Priority 6 Drop 107 Zarlink Semiconductor Inc. Data Sheet OGIC ORT AND RIORITY ...
Page 106
... RPRIORITY – User Define Range Priority Address h0D5, CPU Address: 59e Accessed by CPU, serial interface and MVTX2604 2 C (R/ 7:0 EFINE ANGE (R/ (R/ (R/ (R/ (R/ Range Transmit Priority Drop 108 Zarlink Semiconductor Inc. Data Sheet ...
Page 107
... This is used if the Linkup bit position in the PHY is non- standard. MVTX2604 2 C Address h0C1, CPU Address 517 Address h0C2, CPU Address 518 Address h0C3, CPU Address 519 (R/ Vendor Spc. Reg Addr 109 Zarlink Semiconductor Inc. Data Sheet ...
Page 108
... Disable • 1 – Enable (all ports) When 101110 is detected in DS field (TOS[7:2]), the frame priority is set for 110 and drop is set for 0. MVTX2604 2 C (R/ Duplex bit location 2 C (R/ Mul V- 110 Zarlink Semiconductor Inc. Data Sheet ...
Page 109
... MIIC1 – MII Command Register 1 CPU Address:h604 Accessed by CPU and serial interface only (R/W) Bit [7:0] - MII Data [15:8] Note: Before programming MII command: set FEN[6], check MIIC3, making sure no RDY and no VALID; then program MII command. MVTX2604 111 Zarlink Semiconductor Inc. Data Sheet ...
Page 110
... MIID0 – MII Data Register 0 CPU Address:h607 Accessed by CPU and serial interface only (RO) Bit [7:0] - MII Data [7:0] 14.11.9 MIID1 – MII Data Register 1 CPU Address:h608 Accessed by CPU and serial interface only (RO) Bit [7:0] - MII Data [15:8] MVTX2604 PHY address 112 Zarlink Semiconductor Inc. Data Sheet ...
Page 111
... C Address FF, CPU Address:h60b Accessed by CPU, serial interface and I Bit [7:0]: (Default 0) MVTX2604 2 C (R/ Clock rate Hold Time 01=16 msec 11=64 msec 01 = 100 M/16 = 6.25 MHz 11 = 100 M/64 = 1.5625 MHz 01 = 125 M/128 = 977 KHz 11 = 125 M/1024 = 122 KHz (R/W) 113 Zarlink Semiconductor Inc. Data Sheet ...
Page 112
... When port mirroring is enable, destination port can not serve as a data port. 14.12.3 MIRROR2_SRC – Port Mirror source port CPU Address 702 Accessed by CPU, serial interface (R/W) (Default FF I/O Src Port Select MVTX2604 4 0 Src Port Select 0 0 114 Zarlink Semiconductor Inc. Data Sheet ...
Page 113
... Start BIST (Default = 0) Write ‘1’ followed by ‘0’ to start the device’s built-in self-test. The result is found in the DCR register. Bit [3]: Soft Reset (Default = 0) Write ‘1’ to reset chip MVTX2604 Reset Bist SR SC 115 Zarlink Semiconductor Inc. Data Sheet ...
Page 114
... Bit [2]: 1: BIST in progress 0: BIST not running Bit [3]: 1: RAM Error 0: RAM OK Bit [5:4]: Device Signature 11: MVTX2604 device Bit [7:6]: Revision 00: Initial Silicon 01: XA1 Silicon 10: Production Silicon MVTX2604 BinP 116 Zarlink Semiconductor Inc. Data Sheet ...
Page 115
... Mb MII mode - 01 – mode - 10 – GMII - 11 – PCS Bit [3:2] Giga port 1 strap option - 00 – 100 Mb MII mode - 01 – mode - 10 – GMII - 11 – PCS Bit [7] Chip initialization completed MVTX2604 GIGA1 GIGA0 117 Zarlink Semiconductor Inc. Data Sheet ...
Page 116
... Port 22 Operating mode and Negotiation status - 5’b10111 - Port 23 Operating mode and Negotiation status - 5’b11000 - Port 24 Operating mode/Neg status (CPU port) - 5’b11001 - Port 25 Operating mode/Neg status (Gigabit 1) - 5’b11010 - Port 26 Operating mode/Neg status (Gigabit 2) MVTX2604 118 Zarlink Semiconductor Inc. Data Sheet ...
Page 117
... Reset PCS logic and all TBI registers 1 = Reset Normal operation. Bit [14] Reserved. Must be programmed with “0”. Bit [13] Speed selection (See bit 6 for complete details) MVTX2604 Sig Giga Inkdn FE 119 Zarlink Semiconductor Inc. Data Sheet Refer to the PHY Control 1 0 Fdpx FcEn ...
Page 118
... Reserved. Always read back as “0” Bit [3] Reserved. Always read back as “1” Bit [2] Link Status 1 = Link is up Link is down. Bit [1] Reserved. Always read back as “0”. Bit [0] Reserved. Always read back as “1”. MVTX2604 120 Zarlink Semiconductor Inc. Data Sheet ...
Page 119
... Reserved. Always read back as “0”. Bit [8:7] Pause. Bit [6] Half Duplex 1 = Support half duplex not support half duplex. Bit [5] Full duplex 1 = Support full duplex not support full duplex. Bit [4:0] Reserved. Always read back as “0”. MVTX2604 121 Zarlink Semiconductor Inc. Data Sheet ...
Page 120
... Support 1000 full duplex operation (Default not support 1000 full duplex operation. Bit [14] 1000 Half Duplex 1 = Support 1000 half duplex operation (Default not support 1000 half duplex operation. Bit [13:0] Reserved. Always read back as “0”. MVTX2604 122 Zarlink Semiconductor Inc. Data Sheet ...
Page 121
... 123 Zarlink Semiconductor Inc. Data Sheet ...
Page 122
... 124 Zarlink Semiconductor Inc. Data Sheet ...
Page 123
... CPU Bus-Write Enable internal pull up Input with weak CPU Bus-Read Enable internal pull up Input with weak Chip Select internal pull up Output CPU Interrupt I/O-TS with pullup Frame Bank A– Data Bit [63:0] Output Frame Bank A – Address Bit [20:3] 125 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 124
... Output Frame Bank B – Address Bit [20:3] Output with pull up Frame Bank B Address Status Control Output with pull up Frame Bank B Clock Input Output with pull up Frame Bank B Write Chip Select for one layer SRAM configuration 126 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 125
... MII Management Data I/O – (Common for all MII Ports –[23:0])) Input Reference Input Clock Input with weak Ports [23:0] – Receive Data Bit [1] internal pull up resistors. Input with weak Ports [23:0] – Receive Data Bit [0] internal pull up resistors 127 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 126
... Output, slew Ports [23:0] – Transmit Data Bit [1] Output, slew Ports [23:0] – Transmit Data Bit [0] Output Transmit Data Bit [15:0] [7:0] - GMII [9:0] - TBI [15: Input w/ pull down Receive Data Valid Input w/ pull up Receive Error Input w/ pull down Carrier Sense 128 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 127
... Output w/ pull up Transmit Error Input w/ pull down MII Mode Transmit Clock Output Gigabit Transmit Clock Input w/ pull up Gigabit Reference Clock I/O- TS with pull up LED Serial Interface Output Clock I/O- TS with pull up LED Output Data Stream Envelope 129 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 128
... Reserved - Do not use 10 - Reserved - Do not use 11 – Normal mode. Use external pull up for normal mode Input with pull down Scan Enable Input with pull down 1 – Enable Test mode 0 - Normal mode (open) 130 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 129
... Scans the Collision signal of Home PHY Output Clock for scanning Home PHY collision and link Input/ output Link up signal from Home PHY Input Reset Input Output Reset PHY Default 1 GIGA Link polarity 0 – active low 1 – active high 131 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 130
... FDB RAM depth ( layers) 0 – 2 layer 1 – 1 layer Default 1 CPU installed 0 – CPU installed 1 – CPU not installed Default 1 SRAM Test Mode 0 – Enable test mode 1 – Normal operation 132 Zarlink Semiconductor Inc. Data Sheet Description (4 M total total) ...
Page 131
... P_D[15:13]. Suggested value is 011. Default: 111111 Dedicated Port Mirror Mode. The first 5 bits select the port to be mirrored. The last bit selects either ingress or egress data. 133 Zarlink Semiconductor Inc. Data Sheet Description 0 0 MII ...
Page 132
... Frame Bank A – Address Bit [20:3] Output with pull up Frame Bank A Address Status Control Output with pull up Frame Bank A Clock Input Output with pull up Frame Bank A Write Chip Select for one layer SRAM application 134 Zarlink Semiconductor Inc. Data Sheet Description C Data Clock C Data I/O ...
Page 133
... Output Frame Bank B – Address Bit [20:3] Output with pull up Frame Bank B Address Status Control Output with pull up Frame Bank B Clock Input Output with pull up Frame Bank B Write Chip Select for one layer SRAM application 135 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 134
... MII Management Data I/O – (Common for all MII Ports – [23:0]) Input Reference Input Clock Input with weak internal Ports [23:0] – Receive Data Bit pull up resistors. [1] Input with weak internal Ports [23:0] – Receive Data Bit pull up resistors [0] 136 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 135
... Ports [23:0] – Carrier Sense pull down resistors. and Receive Data Valid I/O- TS with pull up , Ports [23:0] – Transmit Enable slew Strap option for RMII/GPSI Output, slew Ports [23:0] – Transmit Data Bit [1] Output, slew Ports [23:0] – Transmit Data Bit [0] 137 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 136
... Output Transmit Data Bit [15:0] [7:0] - GMII [9:0] - TBI [15: Input w/ pulldown Receive Data Valid Input w/ pullup Receive Error Input w/ pulldown Carrier Sense Input w/ pullup Collision Detected Input w/ pullup Receive Clock Input w/ pullup Receive Data Bit [15:0] [7:0] - GMII [9:0] - TBI [15: 138 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 137
... In managed mode doesn't care Input w/ weak internal Trunk Port Enable in pull down resistors unmanaged mode In managed mode doesn't care Input w/ weak internal Trunk Port Enable in pull down resistors unmanaged mode In managed mode doesn't care 139 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 138
... Input with pull down Scan Enable 0 - Normal mode (open) Input with pull down 1 – Enable Test mode 0 - Normal mode (open) Input System Clock at 100 MHz Power +2.5 Volt DC Supply Power +3.3 Volt DC Supply Power Ground Ground 140 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 139
... SCLK (HPNA SCLK Default 1 CPU Port Mode bit Bus Mode bit Bus Mode Default 1 Memory Size 0 - 256 256 128 128 141 Zarlink Semiconductor Inc. Data Sheet Description (4 M total total) ...
Page 140
... CPU installed 1 – CPU not installed Default 1 SRAM Test Mode 0 – Enable test mode 1 – Normal operation Default: PCS Giga0 Mode: G0_TXEN G0_TXER Default: PCS Giga1 Mode: G1_TXEN G1_TXER 142 Zarlink Semiconductor Inc. Data Sheet Description 0 0 MII GMII 1 ...
Page 141
... P_D[15:13]. Suggested value is 011. Default: 111111 Dedicated Port Mirror Mode. The first 5 bits select the port to be mirrored. The last bit selects either ingress or egress data. 143 Zarlink Semiconductor Inc. Data Sheet Description ...
Page 142
... C13 LA_A[17] J2 A12 LA_A[16] J3 B12 LA_A[15] K1 C12 LA_A[14] K2 A11 LA_A[13] K3 B11 LA_A[12] L1 C11 LA_A[11] L2 144 Zarlink Semiconductor Inc. Data Sheet Signal Name LA_OE0# LA_OE1# LB_D[63] LB_D[62] LB_D[61] LB_D[60] LB_D[59] LB_D[58] LB_D[57] LB_D[56] LB_D[55] LB_D[54] LB_D[53] LB_D[52] LB_D[51] LB_D[50] LB_D[49] LB_D[48] LB_D[47] ...
Page 143
... M[16]_RXD[1] AF23 AF21 M[15]_RXD[1] AG21 AJ19 M[14]_RXD[1] AH21 AF18 M[13]_RXD[1] AF19 AJ17 M[12]_RXD[1] AF17 AJ15 M[11]_RXD[1] AG17 145 Zarlink Semiconductor Inc. Data Sheet Signal Name LB_D[35] LB_D[34] LB_D[33] LB_D[32] LB_D[31] LB_D[30] LB_D[29] LB_D[28] LB_D[27] LB_D[26] LB_D[25] LB_D[24] LB_D[23] LB_D[22] M[4]_RXD[0] M[3]_RXD[0] ...
Page 144
... M[9]_RXD[0] AE14 AE12 M[8]_RXD[0] AJ12 AH11 M[7]_RXD[0] AE11 AH9 M[6]_RXD[0] AJ10 AE9 M[5]_RXD[0] AJ8 AH8 M[6]_TXD[0] G27 146 Zarlink Semiconductor Inc. Data Sheet Signal Name M[11]_CRS_DV M[10]_CRS_DV M[9]_CRS_DV M[8]_CRS_DV M[7]_CRS_DV M[6]_CRS_DV M[5]_CRS_DV M[4]_CRS_DV M[3]_CRS_DV M[2]_CRS_DV M[1]_CRS_DV M[0]_CRS_DV M[23]_TXEN M[22]_TXEN M[21]_TXEN M[20]_TXEN ...
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... M25_RXD[12] M26 W29 M25_RXD[11] L25 W28 M25_RXD[10] N26 W27 M25_RXD[9] N25 Y29 M25_RXD[8] P26 Y28 M25_RXD[7] P25 147 Zarlink Semiconductor Inc. Data Sheet Signal Name M26_RXD[14] M26_RXD[13] M26_RXD[12] M26_RXD[11] M26_RXD[10] M26_RXD[9] M26_RXD[8] M26_RXD[7] M26_RXD[6] M26_RXD[5] M26_RXD[4] M26_RXD[3] M26_RXD[2] M26_RXD[1] M26_RXD[0] M26_TXD[15] ...
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... K18 V15 VSS M10 V16 VSS N10 V17 VSS M20 V18 VSS N20 N14 VSS U10 N15 VSS V10 148 Zarlink Semiconductor Inc. Data Sheet Signal Name M26_RX_DV M26_RX_ER M26_CRS M26_COL M26_RXCLK M26_TX_EN M26_TX_ER M26_TXCLK BIST_DONE/TSTO UT[15] BIST_IN_PRC/TST0 UT[14] MCT_ERR/TSTOUT [13] FCB_ERR/TSTOUT[ 12] CHECKSUM_OK/TS TOUT[11] ...
Page 147
... VSS AD15 U14 VSS AD16 U15 VSS AD17 U16 VSS F13 U17 VSS F14 M12 VSS F15 149 Zarlink Semiconductor Inc. Data Sheet Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VCC VCC VCC VCC VCC ...
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... LA_D[ LA_D[ LA_D[ LA_D[ LA_D[0] H1 C14 LA_A[20] H2 A13 LA_A[19] H3 150 Zarlink Semiconductor Inc. Data Sheet Signal Name Signal Name LA_OE0# LA_OE1# LB_D[63] LB_D[62] LB_D[61] LB_D[60] LB_D[59] LB_D[58] LB_D[57] LB_D[56] LB_D[55] LB_D[54] LB_D[53] LB_D[52] LB_D[51] LB_D[50] LB_D[49] LB_D[48] ...
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... M_CLK AH2 AC29 M[23]_RXD[1] AF2 AE28 M[22]_RXD[1] AC27 AJ27 M[21]_RXD[1] AF29 AF27 M[20]_RXD[1] AG27 AJ25 M[19]_RXD[1] AF26 151 Zarlink Semiconductor Inc. Data Sheet Signal Name LB_D[43] LB_D[42] LB_D[41] LB_D[40] LB_D[39] LB_D[38] LB_D[37] LB_D[36] LB_D[35] LB_D[34] LB_D[33] LB_D[32] LB_D[31] LB_D[30] LB_D[29] LB_D[28] ...
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... M[17]_RXD[0] AE23 AF20 M[16]_RXD[0] AJ22 AE21 M[15]_RXD[0] AJ20 AH19 M[14]_RXD[0] AE20 AH20 M[13]_RXD[0] AJ18 AH17 M[12]_RXD[0] AJ21 152 Zarlink Semiconductor Inc. Data Sheet Signal Name M[19]_CRS_DV M[18]_CRS_DV M[17]_CRS_DV M[16]_CRS_DV M[15]_CRS_DV M[14]_CRS_DV M[13]_CRS_DV M[12]_CRS_DV M[11]_CRS_DV M[10]_CRS_DV M[9]_CRS_DV M[8]_CRS_DV M[7]_CRS_DV M[6]_CRS_DV M[5]_CRS_DV M[4]_CRS_DV ...
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... M25_TXD[4] H26 AC26 M25_TXD[3] H25 AC25 M25_TXD[2] J26 AD26 M25_TXD[1] J25 AD25 M25_TXD[0] K25 U27 M25_RXD[15] K26 153 Zarlink Semiconductor Inc. Data Sheet Signal Name M[12]_TXEN M[11]_TXEN M[10]_TXEN M[9]_TXEN M[8]_TXEN M[7]_TXEN M[6]_TXEN M26_RXD[15] M26_RXD[14] M26_RXD[13] M26_RXD[12] M26_RXD[11] M26_RXD[10] M26_RXD[9] M26_RXD[8] M26_RXD[7] ...
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... VSS N13 V13 VSS K17 V14 VSS K18 V15 VSS M10 V16 VSS N10 V17 VSS M20 154 Zarlink Semiconductor Inc. Data Sheet Signal Name M26_TXD[7] M26_TXD[6] M26_TXD[5] M26_TXD[4] M26_TXD[3] M26_TXD[2] M26_TXD[1] M26_TXD[0] M26_RX_DV M26_RX_ER M26_CRS M26_COL M26_RXCLK M26_TX_EN M26_TX_ER M26_TXCLK ...
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... VSS U24 T18 VSS AD13 U12 VSS AD14 U13 VSS AD15 U14 VSS AD16 U15 VSS AD17 155 Zarlink Semiconductor Inc. Data Sheet Signal Name VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VCC VCC ...
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... M15 VSS P17 VSS P18 VSS R12 VSS -65°C to +150°C -40°C to +85°C +125°C +3 +3.6 V +2. +2. (VCC + 3 -40°C to +85°C AMBIENT 156 Zarlink Semiconductor Inc. Data Sheet Ball No. Signal Name F13 VCC F14 VCC F15 VCC ...
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... Thermal resistance with 1 m/s air flow ja Thermal resistance with 2 m/s air flow 6 ja Thermal resistance between junction and case Thermal resistance between junction and board jb MVTX2604 Min. 2.4 2.0 < VCC) IN 157 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Unit 100 MHz 450 mA 1500 mA V 0.4 V VCC + 2.0 V 0.8 V ...
Page 156
... The TSTOUT[8:0] pins will switch over to the LED interface functionality in 3 SCLK cycles after RESIN# goes high MVTX2604 Tri-Stated R3 Inputs R2 Min. Typ Table 14 - Reset & Bootstrap Timing 158 Zarlink Semiconductor Inc. Data Sheet Outputs Note: RESETOUT# state is then determined by the external pull-up/down resistor Bootstrap pins sampled on rising a edge of RESIN# ...
Page 157
... Recovery Time T DH DATA Hold time (SCLK=100 Mhz) (SCLK=125 Mhz) Min. Max. Min 159 Zarlink Semiconductor Inc. Data Sheet ADDR1 least WH 2 SCLKs T DH DATA Refer to Figure 17 Max. At least 2 SCLK At least 3 SCLK ...
Page 158
... DV DI 2ns Invalid time (SCLK=100 Mhz) (SCLK=125 Mhz) Min. Max. Min LA_CLK L1 L2 LA_D[63:0] 160 Zarlink Semiconductor Inc. Data Sheet ADDR1 least 2 SCLKs DATA Refer to Figure 18 Max. At least 2 SCLK At least 3 SCLK 10 6 ...
Page 159
... L6-max L6-min LA_ADSC# L7-max L7-min L8-max L8-min L9-max L9-min LA_WE# L10-max L10-min LA_OE# -100 MHz Min. (ns) 4 1.5 1 161 Zarlink Semiconductor Inc. Data Sheet Note Max. (ns ...
Page 160
... Figure 21 - Local Memory Interface – Input Setup and Hold Timing Figure 22 - Local Memory Interface - Output Valid Delay Timing MVTX2604 LB_CLK L1 L2 LB_D[63:0] LB_CLK L3-max L3-min LB_D[31:0] L4-max L4-min LB_A[21:2] L6-max L6-min LB_ADSC# L8-max L8-min LB_WE[1:0]# L9-max L9-min LB_OE[1:0]# L10-max L10-min LB_WE# L11-max L11-min LB_OE# 162 Zarlink Semiconductor Inc. Data Sheet ...
Page 161
... Table Characteristics – Local Switch Database SBRAM Memory Interface MVTX2604 -100 MHz Min. (ns) Max. (ns) 4 1.5 1 163 Zarlink Semiconductor Inc. Data Sheet Note ...
Page 162
... M[23:0]_TXEN Output Delay Time M7 M[23:0]_TXD[1:0] Output Delay Time Table Characteristics – Reduced Media Independent Interface MVTX2604 M_CLKI M6-max M6-min M[23:0]_TXEN M7-max M7-min M_CLKI M2 M[23:0]_RXD Min. (ns 164 Zarlink Semiconductor Inc. Data Sheet -50 MHz Note Max. (ns ...
Page 163
... G13-max G13-min M25_TX_EN] G14-max G14-min M25_TX_ER Figure Characteristics- GMII M25_RXCLK M25_RX_DV G5 G6 M25_RX_ER G7 G8 -125 Mhz Min. (ns 165 Zarlink Semiconductor Inc. Data Sheet Note Max. (ns 6 ...
Page 164
... TIMIN T2 T3 Min. (ns) 1 Table 19 - Output Delay Timing Min. (ns Table 20 - Input Setup Timing M26_TXCLK G12-max G12-min G13-max G13-min M26_TX_EN] G14-max G14-min M26_TX_ER Figure Characteristics- GMII 166 Zarlink Semiconductor Inc. Data Sheet TIMAX T2 T3 Max. (ns) Note Ma.x (ns) Note ...
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... Ten Bit Interface - Port B M26_TXCLK M26_TXD [9:0] Figure 31 - Gigabit TBI Interface Transmit Timing MVTX2604 -125 Mhz Min. (ns) Max. (ns 6 TIMIN TIMAX 167 Zarlink Semiconductor Inc. Data Sheet Note ...
Page 166
... Parameter Symbol T2 M26_RXD[9:0] Input Setup Time T3 M26_RXD[9:0] Input Hold Time MVTX2604 Figure 32 - Gigabit TBI Interface Timing Min. (ns) 1 Table 22 - Output Delay Timing Min. (ns Table 23 - Input Setup Timing 168 Zarlink Semiconductor Inc. Data Sheet T3 Max. (ns) Note Max. (ns) Note ...
Page 167
... Parameter LE5 LED_SYN Output Valid Delay LE6 LED_BIT Output Valid Delay Table Characteristics – LED Interface MVTX2604 LED_CLK LE5-max LE5-min LE6-max LE6-min LED_BIT Variable FREQ. Min. (ns 169 Zarlink Semiconductor Inc. Data Sheet Note Max. (ns ...
Page 168
... SCANLINK output valid delay C7 SCANCOL output valid delay MVTX2604 SCANCLK C5-max C5-min C7-max C7-min SCANCOL SCANCLK C1 C2 SCANLINK C3 C4 SCANCOL -25 MHz Min. (ns Table 25 - SCANLINK, SCANCOL Timing 170 Zarlink Semiconductor Inc. Data Sheet Note Max. (ns 30pf 30pf L ...
Page 169
... MDIO input setup time D2 MDIO input hold time D3 MDIO output delay time MVTX2604 MDC D1 D2 MDIO MDC D3-max D3-min MDIO Figure 37 - MDIO Output Delay Timing 1 MHz Min. (ns Table 26 - MDIO Timing 171 Zarlink Semiconductor Inc. Data Sheet Note: Max. (ns ...
Page 170
... Open Drain Output. Low to High transistor is controlled by external pullup resistor. MVTX2604 SCL S2 S1 SDA 2 Figure Input Setup Timing SCL S3-max S3-min SDA 2 Figure Output Delay Timing 50 KHz Min. (ns usec 2 Table Timing 172 Zarlink Semiconductor Inc. Data Sheet Note Max. (ns) 6 usec ...
Page 171
... D0 hold time D3 AutoFd output delay time D4 Strobe low time D5 Strobe high time MVTX2604 Figure 40 - Serial Interface Setup Timing D3-max D3-min Min. (ns Table 28 - Serial Interface Timing 173 Zarlink Semiconductor Inc. Data Sheet D5 D2 Max. (ns) Note 100 pf L ...
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NOTE: 1. CONTROLLING DIMENSIONS ARE DIMENSION "b" IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER 3. SEATING PLANE IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS THE NUMBER OF ...
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