K7N803601B-QC13 Samsung, K7N803601B-QC13 Datasheet
K7N803601B-QC13
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K7N803601B-QC13 Summary of contents
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... K7N803601B K7N801801B 8Mb NtRAM 100 TQFP with Pb & Pb-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ...
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... K7N803601B K7N801801B Document Title 256Kx36 & 512Kx18-Bit Pipelined NtRAM Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Add x32 org part and industrial temperature part 0.2 1. change scan order(1) form 119BGA(x18) 1.0 1. Final spec release 2. Change I form 50mA to 60mA SB2 Change ordering information( remove 225MHz at Nt-Pipelined) 2 ...
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... Note 1. P(Q) [Package type] : P-Pb Free, Q-Pb 2. C(I) [Operating Temperature] : C-Commercial, I-Industrial 3. Support only Pb package Parts. For Pb-Free package, use faster frequency parts. 256Kx36 & 512Kx18 Pipelined NtRAM Access Time (ns) Part Number 3.5 K7N801801B-P(Q) 4.2 K7N801801B-Q 3 3.5 K7N803601B-P(Q) 4.2 K7N803601B RoHS Avail. √ C(I)13 • √ • ...
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... For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. -16 -13 Unit The K7N803601B and K7N801801B are implemented with 6.0 7.5 ns SAMSUNG′s high performance CMOS technology and is avail- 3.5 4 ...
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... Notes : 1. The pin 84 is reserved for address bit for the 16Mb NtRAM and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired 256Kx36 & 512Kx18 Pipelined NtRAM 100 Pin TQFP (20mm x 14mm) K7N803601B(256Kx36) K7N803201B(256Kx32) TQFP PIN NO. SYMBOL 32,33,34,35,36,37,44 V Power Supply(+3.3V) DD 45,46,47,48,49,50,81 ...
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... K7N803601B K7N801801B PIN CONFIGURATION (TOP VIEW) N.C. 1 N. DDQ V 5 SSQ N.C. 6 N.C. 7 DQb 8 8 DQb SSQ V 11 DDQ DQb 12 6 DQb DQb 18 4 DQb DDQ V 21 SSQ DQb 22 2 DQb ...
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... K7N803601B K7N801801B FUNCTION DESCRIPTION The K7N803601B and K7N801801B is NtRAM there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV) ...
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... K7N803601B K7N801801B BEGIN READ READ BURST BURST READ COMMAND DS READ WRITE BURST Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) 256Kx36 & ...
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... K7N803601B K7N801801B TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADV WE BWx ...
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... K7N803601B K7N801801B ASYNCHRONOUS TRUTH TABLE Operation ZZ OE Sleep Mode H L Read L Write L Deselected L ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on Any Other Pin Relative Power Dissipation Storage Temperature Commercial Operating Temperature Industrial Storage Temperature Range Under Bias *Notes : Stresses greater than those listed under " ...
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... K7N803601B K7N801801B DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ Output Leakage Current I OL Operating Current Standby Current I SB1 I SB2 Output Low Voltage(3.3V I/ Output High Voltage(3.3V I/ Output Low Voltage(2.5V I/ Output High Voltage(2.5V I/ Input Low Voltage(3.3V I/O) ...
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... K7N803601B K7N801801B Output Load(A) Dout Zo=50Ω AC TIMING CHARACTERISTICS PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z ...
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... K7N803601B K7N801801B SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SLEEP MODE is dictated by the length of time the High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE ...
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... K7N803601B K7N801801B 256Kx36 & 512Kx18 Pipelined NtRAM - Rev. 5.0 April 2006 ...
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... K7N803601B K7N801801B 256Kx36 & 512Kx18 Pipelined NtRAM - Rev. 5.0 April 2006 ...
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... K7N803601B K7N801801B 256Kx36 & 512Kx18 Pipelined NtRAM - Rev. 5.0 April 2006 ...
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... K7N803601B K7N801801B 256Kx36 & 512Kx18 Pipelined NtRAM - Rev. 5.0 April 2006 ...
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... K7N803601B K7N801801B 256Kx36 & 512Kx18 Pipelined NtRAM - Rev. 5.0 April 2006 ...
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... K7N803601B K7N801801B PACKAGE DIMENSIONS 100-TQFP-1420A 22.00 20.00 #1 0.65 256Kx36 & 512Kx18 Pipelined NtRAM ±0.30 ±0.20 16.00 ±0.30 14.00 ±0.20 (0.83) (0.58) 0.30 ±0.10 0.10 MAX 1.40 1.60 MAX ±0.10 0.05 MIN 0.50 ±0. Units ; millimeters/Inches ° 0~8 + 0.10 0.127 - 0.05 0.10 MAX 0.50 ±0.10 Rev. 5.0 April 2006 ...