K4Y50084UE-JCB3 Samsung, K4Y50084UE-JCB3 Datasheet
K4Y50084UE-JCB3
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K4Y50084UE-JCB3 Summary of contents
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... K4Y50084UE K4Y50044UE K4Y50024UE 512Mbit XDR INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Change History Revision Month Year 0.1 January 2007 0.2 February 2007 1.0 February 2007 - Preliminary TM - Based on the Rambus XDR DRAM Datasheet Version 0.90 - Add current parameters - Add current parameters XDR TM History Rev. 1.0 Feb. 2007 DRAM ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 0.0 Overview The XDR DRAM device is a general-purpose high-performance memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 512Mb XDR DRAM device is a CMOS DRAM organized as 32M words by 16bits. The use of Differential Rambus Signaling Level(DRSL) technology permits 4000/3200/2400 Mb/s transfer rates while using conventional system and board design technologies ...
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... For bin =4, and for bin B, t RC-R RR-D RC-R RR XDR Part Number Bin A K4Y50164UE-JCA2 B K4Y50164UE-JCB3 C K4Y50164UE-JCC4 A K4Y50084UE-JCA2 B K4Y50084UE-JCB3 C K4Y50084UE-JCC4 A K4Y50044UE-JCA2 B K4Y50044UE-JCB3 C K4Y50044UE-JCC4 A K4Y50024UE-JCA2 B K4Y50024UE-JCB3 C K4Y50024UE-JCC4 /t =5 for bin RC-R RR-D RC-R RR-D Rev. 1.0 Feb. 2007 DRAM TM =6. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 3.0 General Description The timing diagrams in Figure 1 illustrate XDR DRAM device write and read transactions. There are three sets of pins used for normal memory access transactions: CFM/CFMN clock pins, RQ11..0 request pins, and DQ15..0/DQN15..0 data pins. The “N” appended to a signal name denotes the complementary signal of a differential pair ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 4.0 Pinouts and Definitions The following table shows the pin assignment of 512Mb x16 XDR DRAM Package. The mechanical dimensions of this package are shown on page 72. Note - Pin # the A1 postion. 16 DQ10 15 DQN10 14 DQ6 13 DQN6 GND GND ...
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... DD 4 RSRV 3 RSRV 2 DQ2 1 DQN2 Top View A ROW COL SAMSUNG K4Y50084UE-JCB3 The pin #1(ROW1, COLA) is located at the A1 position on the top side and the A1 position is marked by the marker Table 1 Package Pinout(Top View) : 100ball FBGA Package DQ0 SDO V GND DD DQN0 RST RSRV GND ...
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... K4Y50084UE K4Y50044UE K4Y50024UE The following table shows the pin assignment of 512Mb x4 XDR DRAM Package. The mechanical dimensions of this package are shown on page 72. Note - Pin # the A1 postion. 16 RSRV 15 RSRV 14 RSRV 13 RSRV GND GND RSRV 3 RSRV ...
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... K4Y50084UE K4Y50044UE K4Y50024UE The following table shows the pin assignment of 512Mb x2 XDR DRAM Package. The mechanical dimensions of this package are shown on page 72. Note - Pin # the A1 postion. Table Package Pinout(Top View) : 100ball FBGA Package 16 RSRV 15 RSRV 14 RSRV 13 RSRV ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 5.0 Pin Description Table2 summarizes the pin functionality of the XDR DRAM device. The first group of pins provide the necessary supply voltages. These include V and GND for the core and interface logic The next group of pins are used for high bandwidth memory accesses. These include DQ15 ... DQ0 and DQN15 ... DQN0 for carrying read and write data signals, RQ11 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 6.0 Block Diagram A block diagram of the XDR DRAM device is shown in Figure2. It shows all interface pins and major internal blocks. The CFM and CFMN clock signals are received and used by the clock generation logic to produce three virtual clock signals : 1/t 2/t , and 16/t ...
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... K4Y50084UE K4Y50044UE K4Y50024UE RQ11..0 VREF 12 1 2/t CYCLE 1:2 Demux 12 12 reg 12 12 Decode COL logic PRE logic 7 6 RD,WR PRE delay delay {0..3}*t CYCLE {0..1}*t CYCLE 2 VTERM Figure 2 : 512Mb (8x4Mx16) XDR DRAM Block Diagram RST,SCK,CMD,SDI CFM CFMN 1/t CYCLE 2/t CYCLE 16 1/t CYCLE REFB,REFr ACT logic ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 7.0 Request Packets A request packet carries address and control information to the memory device. This section contains tables and diagrams for packet formats, field encodings and packet interactions. 7.1 Request Packet Formats There are five types of request packets: 1. ROWA — specifies an ACT command 2. COL — ...
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... K4Y50084UE K4Y50044UE K4Y50024UE CFM CFM CFMN CFMN t RQ11..0 CYCLE ACT RQ11..0 a0 DQ15..0 DQN15..0 ROWA Packet t CYCLE CFM CFMN OP DEL RQ11 RQ10 RQ9 RQ8 RQ7 5 11 rsrv R RQ6 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 7.2 Request Field Encoding Operation code fields are encoded within different packet types to specify commands. Table4 through Table7 provides packet type and encoding summaries. Table4 shows the OP field encoding for five packet types. The COLM and ROWA packets each specify a single command : ACT and WRM ...
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... K4Y50084UE K4Y50044UE K4Y50024UE The REFH/M/L registers are also refreshed to as the REFr registers. Note that only the bits that are needed for specifying the refresh row(11 bits in all) are implemented in the REFr registers - the rest are reserved. Note also that the RA2 ... RA0 field that specifies the refresh bank address is also referred to as BR2...0. See “ ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 7.3 Request Packet Interactions A summary of request packet interaction is shown in Table8. Each case is limited to request packets with commands that perform memory operations(including refresh commands). This includes all commands in ROWA, ROWP, COL, and COLM packets. The commands in COLX packets are described in later sections. See “Maintenance Operations” on page 42. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE The first request is shown along the vertical axis on the left of the table. The second request is shown along the horizontal axis at the top of the table. Each request includes a bank specification “Ba” and “Bb”. The first and second banks may be the same, or they may be different. These two subcases for each interaction are shown along the vertical axis on the letf. There are 32 possible interaction cases altogether. The table gives each case a label of the form “ ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Figure 4 : ACT-, RD-, WR-, PRE-to-ACT Packet Interactions CFM CFM CFMN CFMN RQ11..0 ACT RQ11.. DQ15..0 DQ15..0 DQN15..0 DQN15..0 AAd Case (activate-activate-different bank) a: ROWA Packet with ACT,Ba,Ra b: ROWA Packet with ACT,Bb, ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Figure 5 : ACT-, RD-, WR-, PRE-to-RD Packet Interactions CFM CFMN CFM CFMN RQ11..0 ACT RD RQ11.. DQ15..0 No limit DQN15..0 DQ15..0 DQN15..0 ARd Case (activate-read different bank) a: ROWA Packet with ACT,Ba,Ra b: COL Packet with RD,Bb, ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Figure 6 : ACT-, RD-, WR-, PRE-to-WR Packet Interactions CFM CFM CFMN CFMN ACT WR RQ11..0 RQ11.. limit DQ15..0 DQ15..0 DQN15..0 DQN15..0 AWd Case (activate-write different bank) a: ROWA Packet with ACT,Ba,Ra b: COL Packet with WR,Bb, ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Figure 7 : ACT-, RD-, WR-, PRE-to-PRE Packet Interactions CFM CFM CFMN CFMN ACT PRE RQ11..0 RQ11.. limit DQ15..0 DQ15..0 DQN15..0 DQN15..0 APd Case (activate-precharge different bank) a: ROWA Packet with ACT,Ba,Ra b: ROWP Packet with PRE,Bb ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 7.5 Dynamic Request Scheduling Delay fields are present in the ROWA, COL, and ROWP packet. They permit the associated command to optionally wait for a time of one (or more) t before taking effect. This allows a memory controller more scheduling flexibility when issuing request packets. Figure8 CYCLE illustrates the use of the delay fields ...
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... K4Y50084UE K4Y50044UE K4Y50024UE ACT w/DEL equivalent 0 to ACT w/DEL CFM CFMN RQ11..0 ACT ACT DEL1 DEL0 DQ15..0 DQN15..0 Note DEL value is specified by DELA field. RD w/DEL equivalent w/DEL CFM CFMN RQ11 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 8.0 Memory Operations 8.1 Write Transactions Figure9 shows four examples of memory write transactions. A transaction is one or more request packets (and the associated data packets) needed to perform a memory access. The state of the memory core and the address of the memory access determine how many request packets are needed to perform the access ...
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... K4Y50084UE K4Y50044UE K4Y50024UE CFM CFMN WR WR RQ11.. DQ15..0 D(a1) DQN15..0 t CWD CFM CFMN PRE a3 RQ11..0 t DQ15..0 RP DQN15..0 Transaction CFM CFMN ACT WR WR RQ11..0 a0 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 8.2 Read Transactions Figure10 shows four examples of memory read transactions. A transaction is one or more request packets (and the associated data packets) needed to perform a memory access. The state of the memory core and the address of memory access determine how many request packets are needed to perform the access. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE CFM CFMN RQ11.. DQ15..0 t DQN15..0 CAC Transaction CFM CFMN PRE RQ11.. DQ15..0 DQN15..0 Transaction CFM CFMN ACT RQ11..0 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 8.3 Interleaved Transactions Figure11 shows two examples of interleaved transactions. Interleaved transactions are overlapped with one another; a transaction is started before an earlier one is completed. The timing diagram at the top of the figure shows interleaved write transactions. Each transaction assumes a page-empty access; that is, a bank closed state prior to an access and is precharged after the access ...
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... K4Y50084UE K4Y50044UE K4Y50024UE CFM CFMN RQ11..0 ACT ACT (ACT RQ11.. (COL DQ15..0 RCD-W CC DQN15..0 RQ11..0 t CWD (PRE) RQ11..0 ACT WR WR ACT (ALL Transaction a: WR Ba,Bb,Bc,Bd,Be Transaction b: WR Transaction c: WR are different Transaction d: WR banks ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 8.4 Read/Write Interaction The previous section described overlapped read transactions and overlapped write transactions in isolation. This section will describe the interaction of read and write transactions and the spacing required to avoid channel and core resource conflicts. Figure12 shows a timing diagram (top) for the first case, a write transaction followed by a read transaction. Two COL packets with WR ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 8.5 Propagation Delay Figure 13 shows two timing diagrams that display the system-level timing relationships between the memory component and the memory controller. The timing diagram at the top of the figure shows the case of a write-read-write command and data at the memory component. In this case, the timing will be identical to what has already been shown in the previous sections ...
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... K4Y50084UE K4Y50044UE K4Y50024UE XDR DRAM CFM CFMN WR RQ11..0 a0 DQ15..0 D(a0) t DQN15..0 CWD t CC Transaction a: WR Transaction b: RD Transaction c: WR Controller CFM CFMN WR a0 RQ11..0 DQ15..0 D(a0) DQN15..0 XDR DRAM ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 9.0 Register Operations 9.1 Serial Transactions The serial interface consists of five pins. This includes RST, SCK, CMD, SDI and SDO. SDO uses CMOS signaling levels. The other four pins use RSL signaling levels. RST, CMD, SDI and SDO use a timing window which surrounds the falling edge of SCK. The RST pin is used for initialization ...
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... K4Y50084UE K4Y50044UE K4Y50024UE SCK t CYC,SCK RST Start SCMD CMD ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ SDI (input) SDO (output SCK t CYC,SCK RST Start CMD SCMD ‘ ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 9.4 Register Summary Figure17 through Figure42 show the control register in the memory component. The control registers are responsible for configuring the component’s operating mode, for managing power state transactions, for managing refresh, and for managing calibration operations. A control register may contain up to eight bits. Each figure shows defined bits in white and reserved bits in gray. Reserved bits must be written as 0 and must be ignored when read ...
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... K4Y50084UE K4Y50044UE K4Y50024UE SLE SP[1:0] rsrv rsrv SLE - Serial Load enable field WDSL-path-to-memory disabled WDSL-path-to-memory enabled 2 SP[1:0] - Sub page activation field.(used with SR[1:0]field in ROWA packet Full Page Activation (x16,x8,x4 and x2 WIDTH Half Page Activation (x2 WIDTH only) ...
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... K4Y50084UE K4Y50044UE K4Y50024UE RQL[7: MBR[1:0] reserved reserved reserved Figure Scan Low (RQL) Register Scan Low Register SADR[7:0]: 00000111 RQL[7:0] - Latched value of RQ[7: wire test mode. Figure 23 : Refresh Bank (REFB) Control Register ...
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... K4Y50084UE K4Y50044UE K4Y50024UE R[7: reserved CCVALUE0[5:0] reserved CCVALUE1[5:0] reserved ZCVALUE0[5:0] reserved reserved ZCVALUE1[5:0] reserved reserved Figure 26 : Refresh Low (REFL) Row Register Refresh Low Row Register SADR[7:0]: 00001011 R[7:0] - Refresh row field. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE FZCVALUE0[5:0] reserved reserved FZCVALUE1[5:0] reserved reserved VENDOR[3:0] reserved BB[1:0] RB[2: WTL WTE reserved reserved Figure 32 : Current Fuse Setting 0 (FZC0) Register Current Fuse Setting Register SADR[7:0]: 00010100 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE reserved reserved reserved reserved CWD[3: reserved reserved reserved Note - The partner-definable registers should not be written or read; doing so will produce undefined results. Figure 38 : PLL0 Register ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 10.0 Maintenance Operations 10.1 Refresh Transactions Figure44 contains two timing diagrams showing examples of refresh transactions. The top timing diagram shows a single refresh opera- tion. Bank Ba is assumed to be closed (in a precharged state) when a REFA command is received in a ROWP packet on clock edge T The REFA command causes the row addressed by the REFr register (REFH/REFM/REFL opened (sensed) and placed in the sense amp array for the bank ...
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... K4Y50084UE K4Y50044UE K4Y50024UE CFM CFMN REFA RQ11..0 a0 DQ15..0 DQN15..0 Transaction a: REF Transaction b: REF Bc/Rc = Ba/Ra Transaction c: REF CFM CFMN RQ11.. REFA REFA (ACT) a0 RQ11..0 (PRE) RQ11..0 REFA REFA a0 (ALL) DQ15..0 DQN15.. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 10.3 Calibration Transactions Figure45 shows the calibration transaction diagrams for the XDR DRAM device. There is one calibration operation supported: calibration of the output current level I , each DQi and DQNi pin. OL The output current calibration sequence is shown in the upper diagram. It begins when a period packet (with command “ ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 10.4 Power State Management Figure46 shows power state transition diagrams for the XDR DRAM device. There are two power states in the XDR DRAM: Powerdown and Active. Powerdown state used in applications in which it is necessary to shut down the CFM/CFMN clock signals. In this state, the contents of the storage cells of the XDR DRAM will be retained by an internal state machine which performs periodic refresh operations using the REFB and REFr control registers ...
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... K4Y50084UE K4Y50044UE K4Y50024UE CFM CFMN t CYCLE CMD RQ11..0 a DQ15..0 t CMD-PDN DQN15..0 Transaction a: Last precharge command Transaction b: PDN SCK RST Start 2’h0,SID[5:0] SCMD CMD ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 10.5 Initialization Figure47 shows the topology of the serial interface signals of a XDR DRAM system. The three signals RST, CMD, and SCK are trans- mitted by the controller and are received by each XDR DRAM device along the bus. The signals are terminated to the V through termination components at the end farthest from the controller ...
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... K4Y50084UE K4Y50044UE K4Y50024UE This continues until the last XDR DRAM device drives the SRD input of the controller. Each XDR DRAM device contains a state machine which measures the interval t RST-SDI,00 SID [5:0] field of the SID (Serial Identification) register. This value allows directed read and write transactions to be made to the individual XDR DRAM devices ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Table 11 : XDR DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4/x2 XDR DRAM 16) WDSL Core DQ Pins ‘ Word Load Order Core Word x16 WD[n][15:0] LOGICAL VIEW OF XDR DRAM DQ0 DQ0 DQ0 DQ0 WD[0][15:0] WDSL Word 8 DQ1 DQ1 DQ1 DQ1 WD[1][15:0] WDSL Word 7 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 10.8 Sub-Row (Sub-Page) Sensing The SP[1:0] field of the CFG register controls what fraction of a row is sensed during a ROWA activate operation. This permits the con- troller to reduce the amount of power consumed by normal transactions if a smaller row size can be tolerated by the application. Note that the REFA and REFI activate operations always sense the full row, the SP[1:0] setting does not affect these operations ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 11.0 Special Feature Description 11.1 Write Masking Figure 50 shows the logic used by the XDR DRAM device when a write-masked command (WRM) is specified in a COLM packet. This masking logic permits individual byte of a write data packet to be written or not written according to the value of an eight bit write mask M [7:0] ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Note that other systems might use a data transfer size that is different than the 64 bytes per t example in Figure 50. Figure 51 shows the timing of two successive WRM commands in COLM packets. The timing is identical to that of two successive WR commands in COL packets. The one difference is that the COLM packet includes a M[7:0] field that indicates the reserved bit pattern (for the eight bits of each byte) that indicates that the byte is not to be written ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 11.2 Multiple Bank sets and the ERAW Feature Figure 54 shows a block diagram of a XDR DRAM in which the banks are divided into two sets (called the even bank set and the odd bank set) according to the least-significant bit of the bank address field. This XDR DRAM supports a feature called “Early Read After Write” ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Odd Bank Array Bank 16x16*2 *2 ACT ACT ROW ROW PRE Bank 1 PRE 3 Bank (2 -1) 6 16x16*2 16x16*2 ... Sense Amp Array 6 16x16*2 R/W R/W COL Sense Amp 1 COL Sense Amp 3 (2 -1) 16x16 ... S1[15:0][15:0] WR odd 16x16 Byte Mask (WR) Width Demux (WR) 16x16 ... ... ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 11.3 Simultaneous Activation When the XDR DRAM supports multiple bank sets as in Figure 54, another feature may be supported, in addition to ERAW. This feature is simultaneous activation, and the timing of several cases is shown in Figure 55. The t parameter specifies the minimum spacing between packets with activation commands in XDR DRAMs with a single bank set between packets to the same bank set in a XDR DRAM with multiple bank sets ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 11.4 Simultaneous Precharge When the XDR DRAM supports multiple bank sets as in Figure54, another feature may be supported, in addition to ERAW. This feature is simultaneous precharge, and the timing of several cases is shown in Figure56. The t parameter specifies the minimum spacing between packets with precharge commands in XDR DRAMs with a single bank set between packets to the same bank set in a XDR DRAM with multiple bank sets ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 12.0 Operating Conditions 12.1 Electrical Conditions Table13 summarizes all electrical conditions (temperature and voltage conditions) that may be applied to the memory component. The first section of parameters is concerned with absolute voltage, storage and operating temperatures, and the power supply, reference, and termination voltages. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 12.2 Timing Conditions Table14 summarizes all timing conditions that may be applied to the memory component. The first section of parameters is concerned with parameters for the clock signals. The second section of parameters is concerned with parameters for the request signals. The third section of parameters is concerned with parameters is concerned with parameters for the write data signals. The fourth section of param- eters is concerned with parameters for the serial interface signals ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 13.0 Operating Characteristics 13.1 Electrical Characteristics Table15 summarizes all electrical parameters (temperature, current and voltage) that characterize this memory component. The only exception is the supply current values(I The first section of parameters is concerned with the thermal characteristics of the memory component. Ther second section of parameters is concerned with the current needed by the RQ pins and V The third section of parameters is concerned with the current needed by the DQ pins and voltage levels produced by the DQ pins when driving read data ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 13.3 Timing Characteristics Table 17 summarizes all timing parameters that characterize this memory component. The only exceptions are the core timing parame- ters that are speed-bin dependent. Refer to the Timing Parameters section for more information. The first section of parameters pertains to the timing of the DQ pins when driving read data. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 13.4 Timing Parameters Table18 summarizes the timing parameters that characterize the core logic of this memory component.. These timing parameters will vary as a function of the component’s speed bin. The four sections deal with the timing intervals between packets with, respectively, row- row commands, row-column commands, column-column commands, and column-row commands ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 14.0 Receive/Transmit Timing 14.1 Clocking Figure57 shows a timing diagram for the CFM/CFMN clock pins of the memory component. This diagram represents a magnified view of these pins. This diagram shows only one clock cycle. CFM and CFMN are differential signals: one signal is the complement of the other. They are also high-true signals - a low voltage repre- sents a logical zero and a high voltage represents a logical one ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 14.2 RSL RQ Receive Timing Figure58 shows a timing diagram for the RQ11...0 request pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycle (CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/ CFMN crossing point in which CFM makes its high-voltage-to-low-voltage transition ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 14.3 DRSL DQ Receive Timing Figure59 shows a timing diagram for receiving write data on the DQ/DQN data pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles are shown (CFM and CFMN are the clock signals). Timing events are measured to and from the primary CFM/CFMN crossing point in which CFM makes its high-voltage-to-low -voltage transition ...
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... K4Y50084UE K4Y50044UE K4Y50024UE CFM CFMN t DOFF,MAX t DOFF,MIN t DOFF,DQ0 DQ0 DQN0 t DOFF,DQi DQi 0 DQNi t DOFF,DQ15 DQ15 0 DQN15 Figure 59 : DRSL DQ Receive Waveforms t CYCLE [(j)/8]•t CYCLE IR,DQ IF,DQ [(j)/8]•t CYCLE IR,DQ IF,DQ [(j)/8]•t CYCLE IR,DQ IF, XDR ... ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 14.4 DRSL DQ Transmit Timing Figure60 shows a timing diagram for transmitting read data on the DQ15...0/DQN15...0 data pins of the memory component. This diagram represents a magnified view of these pins and only a few clock cycles are shown (CFM and CFMN are the clock signals). ...
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... K4Y50084UE K4Y50044UE K4Y50024UE CFM CFMN t QOFF,MAX t QOFF,MIN DQ0 t QOFF,DQ0 0 DQN0 [(j+0.5)/8]•t [(j-0.5)/8]•t DQi t QOFF,DQi 0 DQni [(j+0.5)/8]•t [(j-0.5)/8]•t DQ15 t QOFF,DQ15 0 1 DQN15 Figure 60 : RSL DQ Transmit Waveforms t CYCLE [(j+0.5)/8]•t CYCLE [(j-0.5)/8]•t CYCLE OR,DQ OF,DQ CYCLE CYCLE OR,DQ OF,DQ CYCLE CYCLE ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 14.5 Serial Interface Receive Timing Figure61shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the pins only a few clock cycles. The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 14.6 Serial Interface Transmit Timing Figure62 shows a timing diagram for the serial interface pins of the memory component. This diagram represents a magnified view of the pins and only a few clock cycles are shown. The serial interface pins carry low-true signals: a high voltage represents a logical zero and a low voltage represents a logical one. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 15.0 Package Description 15.1 Package Parasitic Summary Table19 summarizes inductance, capacitance, and resistance values associated with each pin group for the memory component. Most of the parameters have maximum values only, however some have both maximum and minimum values. The first group of parameters are for the CFM/CFMN clock pair pins. They include inductance, capacitance, and resistance values. ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Pad Pad Pad C I,DQ R I,DQ Pad Pad C I,CFM R I,CFM Pad Figure 63 : Equivalent Circuits for Package Parasitic L I,RQ C I, PKG, PKG,DQ C I, PKG,CFM Z /2 PKG,CFM C I,CFM R I,CFM L I, XDR TM RQ Pin L 12,RQ RQ Pin L 12,RQ RQ Pin GND Pin ...
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... K4Y50084UE K4Y50044UE K4Y50024UE 15.2 Package Dimensions (100-Ball FBGA) MOLDING AREA (Datum B) 100- ∅0.45 ( Post reflow 0.50 + 0.05 ) (Unit : mm) 14.00 ± 0.10 12.00 0.80 2. Solder ball 0 14.00 ± 0.10 # XDR A #A1 INDEX MARK (Datum A) 0.35 ± 0.05 1.03 ± ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Table of Contents 0.0 Overview ............................................................................................................................................................................................. 3 1.0 Features .............................................................................................................................................................................................. 3 2.0 Key Timing Parameters/Part Numbers ............................................................................................................................................. 4 3.0 General Description ........................................................................................................................................................................... 5 4.0 Pinouts and Definitions ..................................................................................................................................................................... 6 5.0 Pin Description ................................................................................................................................................................................. 10 6.0 Block Diagram .................................................................................................................................................................................. 11 7.0 Request Packets .............................................................................................................................................................................. 13 7.1 Request Packet Formats .............................................................................................................................................................. 13 7.2 Request Field Encoding ............................................................................................................................................................... 15 7.3 Request Packet Interactions ........................................................................................................................................................ 17 7.4 Request Interactions Cases ......................................................................................................................................................... 18 7.5 Dynamic Request Scheduling ...................................................................................................................................................... 23 8.0 Memory Operations ......................................................................................................................................................................... 25 8.1 Write Transactions ....................................................................................................................................................................... 25 8 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE List of Tables Table 1-1. x16 Package Pinout(Top View) : 100ball FBGA Package .................................................................................................... 6 Table 1-2. x8 Package Pinout(Top View) : 100ball FBGA Package .................................................................................................... 7 Table 1-3. x4 Package Pinout(Top View) : 100ball FBGA Package .................................................................................................... 8 Table 1-4. x2 Package Pinout(Top View) : 100ball FBGA Package .................................................................................................... 9 Table 2. Pin Description ......................................................................................................................................................................... 10 Table 3. Request Field Description ....................................................................................................................................................... 13 Table 4 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE List of Figures 1. XDR DRAM Device Write and Read Transactions............. 5 2. 512Mb (8x4Mx16)XDR DRAM Block Diagram .................. 12 3. Request Packet Formats ................................................... 14 4. ACT-, RD-, WR-, PRE-to-ACT Packet Interactions........... 19 5. ACT-, RD-, WR-, PRE-to-RD Packet Interactions............. 20 6. ACT-, RD-, WR-, PRE-to-WR Packet Interactions ............ 21 7 ...
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... K4Y50084UE K4Y50044UE K4Y50024UE Copyright ©Feb. 2007, Samsung Electronics. All rights reserved. Rambus and Rambus logo are trademarks or registered trademarks of Rambus Inc. XDR is a trademark of Rambus Inc. in the United States and other countries. This document contains advanced information that is subject to change by Samsung Electronics without notice Document Version 1 ...