K7D161874B-HC33 Samsung, K7D161874B-HC33 Datasheet
K7D161874B-HC33
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K7D161874B-HC33 Summary of contents
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... K7D163674B K7D161874B Document Title 16M DDR SYNCHRONOUS SRAM Revision History Rev No. History Rev. 0.0 Initial document. Rev. 0.1 Change JTAG DC OPERATING CONDITONS/AC TEST CONDITIONS -to support 1.8~2.5V V Rev. 0.2 Change DC CHARACTERISTICS (Stop Clock Standby Current 100 -> 150 SB1 Rev. 0.3 Change JTAG Instruction Cording - For Reserved Rev. 1.0 ...
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... Ball Grid Array balls on a 1.27mm pitch. ORDERING INFORMATION Part Number K7D163674B-HC37 K7D163674B-HC33 K7D163674B-HC30 K7D163674B-HC27 K7D161874B-HC37 K7D161874B-HC33 K7D161874B-HC30 K7D161874B-HC27 • Registered Addresses, Burst Control and Data Inputs. • Registered Outputs. ) DDQ • Double and Single Data Rate Burst Read and Write. ...
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... K7D163674B K7D161874B FUNCTIONAL BLOCK DIAGRAM SA[0:18]( or SA[0:19]) Address Register CE Clock K,K Buffer Advance B 1 Control Co Write Address B SD/DD 3 Register (2 stage) CE Synchronous Select CE & R/W control R/W LD Internal Clock Generator G PIN DESCRIPTION Pin Name Pin Description K, K Differential Clocks SA Synchronous Address Input Synchronous Burst Address Input (SA ...
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... DDQ DDQ DDQ DDQ DDQ * Mode Pin(6L internally NC. K7D161874B(1Mx18 DDQ DDQ DDQ DDQ H DQ ...
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... K7D163674B K7D161874B Read Operation(Single and Double) During SDR read operations, addresses and controls are registered at the first rising edge of K clock and then the internal array is read between first and second rising edges of K clock. Data outputs are updated from output registers off the second rising edge of K clock ...
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... K7D163674B K7D161874B TRUTH TABLE ↑ ↑ ↑ ↑ ↑ ↑ NOTE : - B(Both) is DIN in write cycle and DOUT in read cycle. Byte write function is not supported. X means "Don't Care" & K are complementary. BURST SEQUENCE TABLE ...
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... K7D163674B K7D161874B BUS CYCLE STATE DIAGRAM READ SDR INCREMENT ADDRESS POWER UP NOTE : 1. State transitions ; B =(Load Address =(Read), B =(Write =(Single Data Rate LOAD NEW ADDRESS WRITE SDR INCREMENT INCREMENT ADDRESS NO OP =(Increment Address, Continue) 1 =(Double Data Rate 512Kx36 & 1Mx18 SRAM ...
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... K7D163674B K7D161874B ABSOLUTE MAXIMUM RATINGS Parameter Core Supply Voltage Relative Output Supply Voltage Relative Voltage on any pin Relative Output Short-Circuit Current(per I/O) Storage Temperature NOTE : Power Dissipation Capability will be dependent upon package characteristics and use environment. See enclosed thermal impedance data. ...
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... K7D163674B K7D161874B PIN CAPACITANCE Parameter Input Capacitance Data Output Capacitance NOTE : Periodically sampled and not 100% tested.(T AC INPUT CHARACTERISTICS Parameter AC Input Logic High AC Input Logic Low Clock Input Differential Voltage V Peak-to-Peak AC Voltage REF AC INPUT DEFINITION (AC REF ...
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... K7D163674B K7D161874B AC TEST OUTPUT LOAD TIMING CHARACTERISTICS PARAMETER SYMBOL Clock Clock Cycle Time t Clock High Pulse Width t Clock Low Pulse Width t Setup Times Address Setup Time t Control(B1,B2,B3) Setup Time t Data Setup Time t Hold Times Address Hold Time t Control(B1,B2,B3) Hold Time ...
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... K7D163674B K7D161874B TIMING WAVEFORMS FOR DOUBLE DATA RATE CYCLES READ NOP READ CONTINUE (burst KHKH KHKL BVKH KHBX AVKH KHAX CHQV KXCV t t CHQZ CHLZ CQ CQ NOTE 1. Q refers to output from address ...
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... K7D163674B K7D161874B TIMING WAVEFORMS FOR SINGLE DATA RATE CYCLES READ READ NOP READ CONTINUE CONTINUE (burst KHKL KLKH KHKH BVKH KHBX AVKH KHAX KXCV t CHQV t t CHQZ CHLZ CQ CQ NOTE : 1 ...
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... K7D163674B K7D161874B IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform- ance with IEEE 1149 ...
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... K7D163674B K7D161874B SCAN REGISTER DEFINITION Part Instruction Register 512Kx36 3 bits bits ID REGISTER DEFINITION Revision Number Part (31:28) 512Kx36 0000 0000 BOUNDARY SCAN EXIT ORDER(x36 ...
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... K7D163674B K7D161874B JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification. JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7D163674B K7D161874B 153 BGA PACKAGE DIMENSIONS 12.50 ±0.10 0.492 ±0.004 14.00 ±0.10 0.551 ±0.004 TOP VIEW 153 BGA PACKAGE THERMAL CHARACTERISTICS Parameter Junction to Ambient(at still air) Junction to Case Junction to Board NOTE : 1. Junction temperature can be calculated 512Kx36 & 1Mx18 SRAM 0.60 ±0.10 0.024 ± ...