CXD2303AQ Sony, CXD2303AQ Datasheet
CXD2303AQ
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CXD2303AQ Summary of contents
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... MSPS Video A/D Converter with clamp function Description The CXD2303AQ is an 8-bit 3-channel CMOS A/D converter for video with synchronizing digital clamp function. The adoption of 2 step-parallel method achieves low power consumption and a maximum conversion rates of 50 MSPS. Features • Resolution : 8 bit±1/2 LSB (DL) • ...
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... Digital Clamp 9 Circuit 8 Data Selector Digital Clamp 9 Circuit 8 Digital Clamp 9 Circuit Clamp Control —2— CXD2303AQ (LSB (MSB) 44 XAOE 3 B0 (LSB (MSB) 10 Latch 45 XBOE 73 C0 (LSB (MSB) 46 XCOE 21 TGR CTL0 ...
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... Pin Configuration —3— CXD2303AQ ...
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... —4— CXD2303AQ Description Digital power supply +3.3 V Digital output. A0 (LSB (MSB) B0 (LSB (MSB) C0 (LSB (MSB) Trigger output. See the Tables and Timing Chart II described in the Output Format section. Digital ground. ...
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... Pull-down resistors are incorporated. Controls the digital output mode switching timing. The mode is switched by detecting the transition point where this pin changes from Low to High. See the Mode Tables and Timing Charts for details. A pull-down resistor is incorporated. —5— CXD2303AQ Description ...
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... These pins are not synchronized with the clock input signal. Pull-down resistors are incorporated. Clamp enable. When this pin is Low, the clamp circuit does not operate. When this pin is High, the clamp circuit operates. A pull-down resistor is incorporated. —6— CXD2303AQ Description ...
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... V 255 BRB CRB tr tf 4ns 4ns 90% 10 Timing Chart I-1. tf=4.5ns 90% 1.3V 10 1.3V 10 90% 1.3V Timing Chart I-2. —7— CXD2303AQ LSB : : ...
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... CXD2303AQ ...
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... MHz MHz IN F =10 MHz IN F =20 MHz MHz sin wave IN (2 V+E – each channel OT OB – each channel OT OB —9— CXD2303AQ =0 =2.5 V, Ta=25 ° Min. Typ. Max. Unit 0.5 50 MSPS 60 MHz 100 ±0.3 ±0.5 LSB ±0.7 ±1.5 –50 – ...
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... DD VOL=0.4 V Ta=– °C XOE=0 V VOH=DV –0 =3 VOL=0.4 V Ta=– °C XOE=3 V VOH= 5 VOL=0 V Ta=– °C —10— CXD2303AQ =0 =2.5 V, Ta=25 ° Min. Typ. Max. Unit 80 100 ...
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... = XOE =3 CTL0 to 2, CLP, SY CLP CLK conversion SY Tri-state output measurement circuit Measurement point To output pin —11— CXD2303AQ Min. Typ. Max. Unit DV DD –0.8 0 –0.8 0.4 =0 =2.5 V, Ta=25 ° Min. Typ. Max. Unit 8 ...
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... TO 111··· TTL 8 8 DUT CXD2303AQ ECL 2.5V 0.5V TTL ECL 2. Data A 0.5V out V OL —12— CXD2303AQ +5V 2. CLK 0. CX20202A-1 8 ...
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... The same as for measuring the channels B and C. Description of Operation 1. Output Format The CXD2303AQ can select six different types of output formats through a combination of the CTL0, CTL1 and CTL2 inputs as shown in the table below. Output is synchronized to the SY input signal transition from Low to High. ...
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... CXD2303AQ ...
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... Low —15— CXD2303AQ ...
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... High Low High —16— CXD2303AQ ...
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... HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ High Low High Low High HiZ : High impedance —17— CXD2303AQ ...
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... HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ High Low High Low High HiZ : High impedance —18— CXD2303AQ ...
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... HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ High Low High HiZ : High impedance —19— CXD2303AQ ...
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... HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ HiZ High Low High HiZ : High impedance —20— CXD2303AQ ...
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... Mode #6, 7 simple boundary scan 1 and 2 The CXD2303AQ has a simple boundary scan function Note : CLK and SY must be set. 2. Clamp Function The following two points should be noted when using the digital clamp circuit. -The clamp pulse must be supplied externally. ...
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... Timing III (When SEL=low) Photo 2. Response waveform of clamp circuit (F =50 MSPS, clamp pulse is NTSC SYNC and CLK reference data is 128) Upper: Analog input pin waveform (H: 200 µs/div V/div.) Lower: Vertical hold pulse (H: 200 µs/div., V: 500 mV/div.) —22— CXD2303AQ ...
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... Fig. 1. 8-bit ADC block diagram Lower Lower Sampling Encoder Comparator (4bits) (4bits) Upper Data Latch Lower Lower Sampling Encoder Comparator (4bits) (4bits) Upper Upper Upper Sampling Encoder Data Comparator (4bits) Latch (4bits) —23— CXD2303AQ Data0 (LSB) Data1 Data2 Data3 Data4 Data5 Data6 Data7 (MSB) ...
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... Data0 to Data7 3. 8-bit ADC Operation (See Fig.1 and Timing Chart IV) 1) The CXD2303AQ includes 3 channels of the 8-bit A/D converter. This converter has the 2-step parallel system, composed of a 4-bit upper comparator and two 4-bit lower comparator blocks. The reference voltage that is equal to the voltage between RT-RB/16 is constantly applied to the upper 4-bit comparator block ...
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... XBOE, and Pins (C0 to C7) with XCOE, respectively. in series between the amplifier output and A/D input. When the input =about 2.5 V and V =about 0 activated by shorting ARTS, BRTS RB , respectively Pins (B0 to B7) have the same DD —25— CXD2303AQ , and these SS ...
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... CXD2303AQ ...
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... CXD2303AQ ...
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... CXD2303AQ ...
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... Input frequency vs. Supply current 100 85 = =DV =5V DD –1 – 0.1 —29— CXD2303AQ F =50MHz C NTSC ramp wave input AV = CLE=High Ta=25°C 4.75 5 5.25 Supply voltage [V] F =50MHz C Sine wave 1.6Vp-p AV =DV = Ta=25°C CLE=Low 0.1 ...
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... Ambient temperature [°C] Load capacitance vs. Output data delay 14 12 tpLH tpHL Load capacitance [pF] Analog input voltage vs. Input current 80 0 –80 5.5 0.5 Analog input voltage V —30— CXD2303AQ F =50MHz C AV =DV = =2Vp-p IN Ta=25° Fc=10MHz AV = =3.3V DD CL=15pF 25 ...
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... Input frequency vs. Cross talk F =50MHz =1.6Vp-p IN Ta=25° 0 Input frequency F [MHz] IN =DV = —31— CXD2303AQ ...
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... CXD2303Q Evaluation Board Evaluation boards are available for the CMOS converter CXD2303AQ. Block Diagram Digital Circuit Mount Portion Analog output Digital Circuit Mount Portion Characteristics • Resolution • Maximum conversion rate • Supply voltage Supply voltage Item Min. Typ –5 V Clock input Either should be used ...
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... Analog Output (CXD1178Q) Item Min. Typ. Analog output 1.8 2.0 Full-scale 0 1.5 output ratio ( ) Full-scale output ratio = Average of the full-scale voltage of each channel Output Format (CXD2303AQ) The table shows the output format of AD converter. Analog input Step voltage MSB ART BRT CRT ...
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... C20 0.1 µF C21 47 µF C22 0.1 µF C30A 470 µF C31A µF C30A 0.1 µF C50 0.1 µF C51 0.1 µF C52 0.1 µF C53 0.1 µF Others Connector BNC-LR-PC-3 (Hirose Electric Co.,Ltd.) DIP SW —34— CXD2303AQ Max. Unit V 1100 ns 1100 ns 11 ...
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... CXD2303AQ ...
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... R34B and R34C open, Q32A, Q32B, Q32C can also be used as buffer. Use the open space for the bias circuit. 5. Clamp pulse latch The latch is incorporated in the CLP pin of the CXD2303AQ. 6. Peripheral through hole There is a group of through holes on the analog input, output and logic. They are to be used when mounting additional circuits to the evaluation board ...
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... DETAIL A SONY CODE EIAJ CODE JEDEC CODE 80PIN QFP (PLASTIC) 23.9 ± 0 0.15 0.35 – 0.1 M 0.2 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-80P-L01 QFP080-P-1420 LEAD MATERIAL PACKAGE MASS —37— CXD2303AQ + 0.1 0.15 – 0.05 0. 0.2 0.1 – 0.05 + 0.35 2.75 – 0.15 EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g ...