AM79C984AJC Advanced Micro Devices, AM79C984AJC Datasheet
AM79C984AJC
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AM79C984AJC Summary of contents
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... Section 9 of the IEEE 802.3 standard and Twisted Pair Transceiver functions complying with the 10BASE-T standard. This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Am79C984A J Valid Combinations Am79C984A ...
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BLOCK DIAGRAM Am79C984A 3 ...
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RELATED AMD PRODUCTS Part No. Description Am7990 Local Area Network Controller for Ethernet (LANCE) Am7992B Serial Interface Adapter (SIA) Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted ...
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TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Enable Link Pulse (Per TP Port ...
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CONNECTION DIAGRAM (PL 084 REXT 13 AVSS DI+ 14 DI– VDD 17 CI+ CI– 18 AVSS 19 20 DO+ 21 DO– AMODE 22 VDD 23 24 DVSS VDD 25 VDD 26 27 VDD ...
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CONNECTION DIAGRAM (PQR100) RXD3– REXT 5 AVSS 6 DI+ 7 DI– 8 VDD 9 CI+ 10 CI– 11 AVSS 12 DO+ 13 DO– 14 AMODE 15 VDD 16 DVSS 17 VDD 18 VDD ...
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LOGIC SYMBOL Expansion Port Test and Control Port LOGIC DIAGRAM LED Port Control Port Twisted Pair Port DAT TXD+ JAM TXD– ACK RXD+ COL RXD– SELO ...
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PIN DESIGNATIONS (PL 084) Listed by Pin Number Pin No . Pin Name Pin TXD3+ 2 TXD3- 3 VDD 4 RXD0+ 5 RXD0- 6 RXD1+ 7 RXD1- 8 RXD2+ 9 RXD2- 10 RXD3+ 11 RXD3- 12 REXT ...
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PIN DESIGNATIONS (PQR100) Listed by Pin Number Pin No . Pin Name Pin RXD3 REXT 6 AVSS 7 DI+ 8 DI- 9 VDD 10 CI+ 11 CI- 12 AVSS 13 ...
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PIN DESCRIPTION AUI Port DI+, DI– Data In Differential Input DI are differential, Manchester receiver pins. The sig- nals comply with IEEE 802.3, Section 7. DO+, DO– Data Out Differential Output DO are differential, Manchester output driver pins. The signals ...
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I/O and must be pulled to VDD via a minimum equiv- alent resistance When the eIMR device expan- sion port is configured for IMR+ mode, COL is an input driven by an external arbiter. Control Port ...
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AVSS Analog Ground Ground Pin This pin is the ground reference for the differential receivers and drivers DVSS Digital Ground Ground Pin This pin is the ground reference ...
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FUNCTIONAL DESCRIPTION The Am79C984A eIMR device is a single-chip imple- mentation of an IEEE 802.3/Ethernet repeater (or hub offered with four integral 10BASE-T ports plus one RAUI port comprising the basic repeater. The eIMR de- vice is also ...
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Alternative reconnection algorithm—A data packet longer than 512-bit times (nominal) is transmitted by the partitioned port without a collision. A partitioned port can also be reconnected by disabling and re-enabling the port. All TP ports use the same reconnection ...
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Proper termination is shown in the Systems Applications section. The receiver’s threshold voltage can be programmed to an extended-distance mode. In this mode, the differen- tial receiver’s threshold is reduced to allow a longer cable than the ...
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Table 2. LED Attribute-Monitoring Program Options LED Control Global LEDs LDC LDC LDC LDGA CRS CRS CRS 260-ms blk ...
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LED Interface ACT[0] ACT[1] ACT[2] ACT[3] ACT[4] ACT[5] ACT[6] ACT[7] Table 3 shows ACT as a function of the percentage 0-7 of network utilization. The table uses a scale that is more sensitive at low utilization levels. 100% utilization ...
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Expansion Bus Interface The eIMR device expansion bus allows multiple eIMR devices to be interconnected. The expansion bus supports two modes of operation: internal arbitration mode and IMR+ mode. The internal arbitration mode uses a modified daisy-chain scheme to eliminate ...
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SELI_0 SELO SELI_1 SELI_0 SELO SELI_1 SELI_0 SELO SELI_1 SELI_0 SELO SELI_1 Figure 5. Internal Arbitration—eIMR Devices in Cascade Control Functions The eIMR device receives control commands in the form of byte-length data on the serial input ...
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Command/Response Timing Figure 6 shows the command/response timing. At the . SCLK Control Commands The following section details the operation of each con- trol commands available in the eIMR ...
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Table 5. Control Port Command Summary Commands Set (Write Commands) eIMR Chip Programmable Options Alternate AUI Partitioning Algorithm Alternate TP Partitioning Algorithm AUI Port Disable AUI Port Enable TP Port Disable TP Port Enable Disable Link Test Function (per TP ...
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SET (Write Commands) Chip Programmable Option SI Data 0000 10S0 SO Data None The eIMR chip programmable option can be enabled (or disabled) by setting (or resetting) the S bit in the command string. S AUI SQE Test Mask Setting ...
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Disable Automatic Receiver Polarity Reversal (Per TP Port) SI Data 0110 00## SO Data None This command disables the Automatic Receiver Polarity Reversal function for the TP port designated by the two least-significant bits in the command byte. If this ...
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Enable Software Override of Bank B LEDs (Per Port - AUI and TP, Global) SI Data 1100 #### SO Data None This command forces the LEDs in Bank B to blink. In- dividual LEDs and combinations of LEDs can be ...
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Link Test Status of TP ports SI Data 1101 0000 SO Data 0000 L3.. Port n in Link Test Failed port n in Link Test Passed where ...
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TXD+ 110 TXD- RXD+ 100 RXD– eIMR 1:1 TXD0+ 110 TXD0– 1:1 RXD0+ 100 RXD0– 1:1 TXD1+ 110 TXD1– 1:1 RXD1+ 100 RXD1– 1:1 TXD2+ 110 TXD2– 1:1 ...
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MAC Interface The eIMR device can be connected directly to a MAC through the AUI port. This requires that the AUI port be configured in the reverse mode and connected as shown in Figure 10a. Notice that DI is connected ...
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In a multiple eIMR system, the reset signal must be synchronized to CLK.) 74LS74 RST MHz OSC Figure 11. eIMR Internal Arbitration Mode Connection eIMR SELI_0 SELO SELI_1 ...
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Visual Status Display LDA/B[4:0] and LDGA/B provide visual status indicators for the eIMR. LDA/B[4:0] displays Link, Carrier Sense, Collision, and Partition information for the TP and AUI ports. LDGA/B display global Carrier Sense, Collision, and Jabber information multiple ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . – +150 C Ambient Temperature Under Bias . . . . +70 C Supply Voltage referenced ...
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DC CHARACTERISTICS (continued) Parameter Symbol Parameter Description Twisted Pair Ports (Continued) V RXD Positive Squelch Threshold TSQ+ (peak) V RXD Negative Squelch Threshold TSQ– (peak) V RXD Post-Squelch Positive THS+ Threshold (peak) V RXD Post-Squelch Negative THS– Threshold (peak) V ...
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SWITCHING CHARACTERISTICS Parameter Symbol Parameter Description Clock and Reset Timing t CLK Clock Period CLK t CLK Clock High CLKH t CLK Clock Low CLKL t CLK Rise Time CLKR t CLK Fall Time CLKF t Reset Pulse Width after ...
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SWITCHING CHARACTERISTICS (continued) Parameter Symbol Parameter Description Twisted Pair Port Timing t CLK Rising Edge to TXD Transition Delay TXTD t Transmit End of Transmission TETD t RXD Pulse Width Maintain/Turn-off PWKRD Threshold t Idle Signal Period PERLP t Idle ...
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KEY TO SWITCHING WAVEFORMS SWITCHING WAVEFORMS CLK WAVEFORM INPUTS Must be Steady May Change from May Change from Don’t Care, Any Change ...
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SWITCHING WAVEFORMS (continued) SCLK SI t SODLY SO CLK RST TCLK Note: TCLK represents internal eIMR timing AMODE, SELI_0 RST SCLKR t SCLK t t SCLKH SCLKL t ...
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SWITCHING WAVEFORMS (continued) CLK TCLK SELO ACK COL DAT/JAM Note: TCLK represents internal eIMR timing CLK TCLK SELO ACK COL DAT/JAM Note: TCLK represents internal eIMR timing ...
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SWITCHING WAVEFORMS (continued) CLK TCLK SELO ACK COL IN DAT/JAM Note: TCLK represents internal eIMR timing CLK t DOTD DO+ DO – t PWKDI (t PWKCI DI+ ( ASQ t PWODI (t ) PWOCI ...
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SWITCHING WAVEFORMS (continued CLK TXD+ TXD– t PWLP V TSQ+ RXD+/– V TSQ– TXETD Figure 23. TP Ports Output ...
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SWITCHING TEST CIRCUIT Pin Test Point V SS Figure 26. Switching Test Circuit Am79C984A 20650A-32 20650B-31 41 ...
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PHYSICAL DIMENSIONS PL 084 84-Pin Plastic LCC (measured in inches) 1.185 1.195 1.150 1.156 Pin 1 I.D. 1.185 1.195 1.150 1.156 .026 .050 REF .032 TOP VIEW .062 ...
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PHYSICAL DIMENSIONS PQR100 100-Pin Plastic Quad Flat Pack Pin 100 12.35 REF Pin 1 I.D. Pin 30 2.70 2.90 0.25 MIN 17.00 17.40 13.90 14.10 Pin 50 0.65 BASIC ...
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... Copyright © 1998 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am186, Am386, Am486, Am29000, b IMR, eIMR, eIMR+, GigaPHY, HIMIB, ILACC, IMR, IMR+, IMR2, ISA-HUB, MACE, Magic Packet, PCnet, PCnet- FAST , PCnet- FAST +, PCnet-Mobile, QFEX, QFEXr, QuASI , QuEST, QuIET, TAXIchip, TPEX, and TPEX Plus are trademarks of Advanced Micro Devices, Inc ...