82562ET Intel Corporation, 82562ET Datasheet
82562ET
Specifications of 82562ET
Related parts for 82562ET
82562ET Summary of contents
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... Mbps Platform LAN Connect (PLC) Networking Silicon Product Features IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface IEEE 802.3u Auto-Negotiation support Digital Adaptive Equalization control Link status interrupt capability XOR tree mode support 3-port LED support (speed, link and ...
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... Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82562ET PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... Pg. 35, changed the Rev. number on the 82562 Pinout symbol to 1.0. Advance Information Datasheet release (Intel Secret). • Modified Table 1 “82562ET Hardware Configuration” to add one row for XOR Tree and include column for comments. • Updated the descrition of the Activity LED signal in Section 3.6, “LED Pins”. ...
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... Networking Silicon iv Datasheet ...
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... DC Characteristics ............................................................................................... 9 4.2.1 X1 Clock DC Specifications ..................................................................... 9 4.2.2 LAN Connect Interface DC Specifications .............................................10 4.2.3 LED DC Specifications .......................................................................... 10 4.2.4 10BASE-T Voltage and Current DC Specifications ............................... 10 4.2.5 100BASE-TX Voltage and Current DC Specifications ..........................11 5.0 Package and Pinout Information ...................................................................................... 13 5.1 Package Information ........................................................................................... 13 5.2 Pinout Information ............................................................................................... 14 5.2.1 82562ET Pin Assignments .................................................................... 14 5.2.2 82562ET Shrink Small Outlying Package Diagram ............................... 15 Datasheet Networking Silicon — 82562ET v ...
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... Networking Silicon vi Datasheet ...
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... Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. The 82562ET complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82563ET also includes a PHY interface compliant to the current platform LAN connect interface ...
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... Networking Silicon 1.4 Product Code The product ordering code for the 82562ET is: DA82562ET. 2 Datasheet ...
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... Architectural Overview The 82562ET is a highly integrated Platform LAN Connect device that combines a 10BASE-T and 100BASE-TX physical layer interfaces. The 82562ET supports a single interface fully compliant with the IEEE 802.3 standard. Figure 1. 82562ET Block Diagram RDN/RDP TDN/ TDP The 8252ET is a 3.3 V device in a 48-pin Shrink Small Outline Package (SSOP). This document describes the architecture of the device in all modes of operation ...
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... Networking Silicon Figure 2. 82562ET Solution Overview VRM IDE Primary UltraDMA/33 IDE Secondary USB Port 1 USB USB Port 2 AMC97 Audio/ AC97 Link Modem 4 Procesor Clock 2 RIMM MCH Modules PCI Control Bus ICH2 PCI Address/Data Bus Control Address/Data LPC Bus SIO ...
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... Datasheet Description Input pin to the 82562ET. Output pin from the 82562ET. Multiplexed input and output pin to and from the 82562ET. Multi-level analog pin used for input and output. Bias pin used for ground connection through a resistor or an external voltage reference. Digital power or ground pin for the 82562ET. ...
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... O LAN Connect Receive Data. The LAN Connect receive pins are used to transfer data from the 82562ET to the MAC device. These pins are used to move received data and real time control and management data. They also move out of band control data from the PHY to the MAC. These pins are synchronous to LAN_CLK ...
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... Type I Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted high, and the 82562ET advertises only 10BASE-T technology during Auto-Negotiation processes in this state. Otherwise, the 82562ET advertises all of its technologies. Note: ADV10 has an internal pull-down resistor. ...
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... Networking Silicon Pin Pin Name Number ISOL_TEX 29 TOUT 26 TESTEN 21 3.8 Power and Ground Connections Pin Pin Name Number VCC 1, 25 VCCP 36, 40 VCCA 2, VCCA2 7, VCCT 9, 12, 14, 17 VSS 8, 13, 18 24, 48 VSSP 33, 38 VSSA 3 VSSA2 6 VCCR 19, 23 VSSR 20 Type I Test Execute. The Test Execute signal sets the device into asynchronous ...
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... Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 3.45 V Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V Stresses above the listed absolute maximum ratings may cause permanent damage to the 82562ET device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... Networking Silicon 4.2.2 LAN Connect Interface DC Specifications Table 4. LAN Connect Interface DC Specifications Symbol Parameter Input/Output V CCJ Supply Voltage V Input Low Voltage IL Input High V IH Voltage Input Leakage I IL Current Output Low V OL Voltage Output High V OH Voltage Input Pin C IN ...
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... Input Differential V Reject Peak IDR100 Voltage Input Common V ICM100 Mode Voltage NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN. Datasheet Networking Silicon — 82562ET Condition Min Typical MHz f 10 MHz 585 5 MHz f 10 MHz ...
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... Networking Silicon 12 Datasheet ...
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... Package and Pinout Information 5.1 Package Information The 82562ET is a 48-pin Shrink Small Outlying Package (SSOP). The Package dimensions are shown in Figure 3. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local sales office. ...
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... Networking Silicon 5.2 Pinout Information 5.2.1 82562ET Pin Assignments Table 10. 82562ET Pin Assignments Pin Pin Name Number 1 VCC 2 VCCA 3 VSSA 4 RBIAS10 5 RBIAS100 6 VSSA2 7 VCCA2 8 VSS 9 VCCT 10 TDP 11 TDN 12 VCCT 14 Pin Pin Pin Name Number Number 13 VSS 25 14 VCCT 26 15 RDP 27 16 ...
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... Shrink Small Outlying Package Diagram Figure 4. 82562ET Pin Out Diagram VCC (DPS) VCCA (APS) VSSA (APS) RBIAS10 (B) RBIAS100 (B) VSSA2 (APS) VCCA2 (APS) VSS (DPS) VCCT (APS) 10 TDP (MLT) 11 TDN (MLT) 12 VCCT (APS) 13 VSS (DPS) 14 VCCT (APS) 15 RDP (MLT) 16 RDN (MLT) ...